Abstract: A method for adjusting the PCI Express lane ordering is disclosed, comprising the following steps. The first packet associated with a first PCI Express lane ordering is sent to the peripheral device. The peripheral device replies the second packet associated with the second PCI Express lane ordering. Whether the PCI Express lane ordering is correct is determined in response to said second packet. The first PCI Express lane ordering is adjusted while the first PCI Express lane ordering does not match the second PCI Express lane ordering. Preferably, the adjusted PCI Express lane order matches the normal order or the reverse order. Then, reset and reinitialize the peripheral device. The resetting step can be accomplished by sending reset packets, or changing the common mode voltage level in order to reset the bridge chipset of the PC.