Abstract: A flash translation layer apparatus is disclosed. The flash translation layer apparatus coupled to a flash memory and a reading and writing controller, respectively. The flash translation layer apparatus includes an instruction register, a logical address register, a data register, a first auxiliary controller, a microprocessor, an address converting unit, a second auxiliary controller, a flash address register and an adjustable translation layer unit. Furthermore, the adjustable translation layer unit regards the block as a unit for a coarse-grained address translation table and regards the pages as a unit for a fine-grained address translation table, respectively. Therefore, the present invention can provide capabilities of reducing the spaces and the times of a null data collection procedure and increasing the efficiency when a logical address corresponds to a physical address.

Abstract: A method for managing medium access control (MAC) address and related apparatus are provided, including an MAC address learning method and an MAC addresses inquiring method. The learning method includes the steps of: mapping an MAC address to a designated slot and a companion slot in an address table; if said designated slot being empty, learning said MAC address into said designated slot; and if said designated slot being non-empty, said companion slot being empty and the content of said designated slot being non-static, moving the content of said designated slot to said companion slot and modifying a bit of the higher part of said MAC address in said companion slot and learning said MAC address into said designated slot.

Abstract: The present invention discloses a serial ATA (SATA) card reader control system and a controlling method of the same. The SATA card reader control system and the controlling method are capable of identifying a flash memory card type which is intended to be accessed by an SATA host based on a 4-bit Port Multiplier port information defined in SATA Frame Information Structure (FIS). Accordingly, the SATA host with usage of only one physical transport can access at most fifteen different types of flash memory cards. And a SATA transmission interface can be utilized in a multi-card reader in order to access various types of flash memory cards and increase the transmission speed between the SATA host and the multi-card reader.

Abstract: A management method for reducing the utilization rate of random access memory (RAM) while reading data from or writing data to the flash memory is disclosed. A physical memory set is constructed from a plurality of physical memory blocks in the flash memory. A logical set is constructed from a plurality of logical blocks wherein the data stored in the logical set are stored in the physical memory set. Further, the data stored in each of the logical blocks are stored in one number of physical memory blocks. A mapping table is constructed and includes a hash function, a logical set table, a physical memory set table, and a set status table for managing the relationship among the physical memory sets, physical memory blocks, and logical blocks while reading data from or writing data to the flash memory.

Abstract: A cache device comprises a hard disk, cache control unit and at least one flash memory, whereby the cache control unit controlling and regulating the flash memory as the hard disk cache device. The present invention method is defined by setting up a management table to manage each corresponding logical block address of the flash memory through a cache data read-out step and cache data write-in step in order to manage the cache read or write action of the flash memory on the hard disk. In addition, the step of recycling a cache space and replacing cache temporary data storage is to remove and replace temporary cache and storage space within the flash memory on the hard disk. Moreover, the step of reconstruction management table is provided to reconstruct management table loss or damage caused by power outage or irregular shut-down of the computer and will be able to provide flash memory on the hard disk cache control.

Abstract: A caching device is positioned between a memory read/write controller and a flash memory, which contains an instruction register, a logical address register, a data register, a pair of auxiliary controllers, a microprocessor, an address translation unit, a flash memory address register, a caching control unit, and a caching instruction and data buffer area. Among them, the microprocessor is the core of the caching device responsible not only for the reading and writing the flash memory but also for the caching operation for logical and physical address translation. The caching control unit is a programmable device containing the instruction and data for caching the logical and physical address mapping. The caching instruction and data buffer area temporarily stores the caching instruction and data used by the caching control unit.

Abstract: A method for performing a static wear leveling on a flash memory is disclosed. Accordingly, a static wear leveling unit is disposed with a block reclamation unit of either a flash translation layer or a native file system in the flash memory, and utilizes less memory space to trace a distribution status of block leveling cycles of each physical block of the flash memory. Based on the distribution record of the block leveling cycles, the number of the leveling cycles less than a premeditated threshold would be found while the system idles. Then the static wear leveling unit requests the block reclamation unit to level the found blocks. Before leveling the found block, the rarely updated data is compelled to move from one block to another block which is leveled frequently, whereby accurate wear leveling cycles for the blocks can be averaged extremely.

Abstract: A method of facilitating reliably accessing flash memory is provided. During the write-in process, the present invention utilizes the steps of coding write-in data to generate extra data, and then generating the first error correction code by performing an error-correcting operation on the write-in data and the extra data. Finally, store the N write-in data and the generated K extra data into the data area and the first ECC into the spare area. During read process, the present invention utilizes the steps of reading data from the data area of the target flash-memory page to generate the second ECC, counting with the counter a number of bit differences between the first ECC and the second ECC, and selecting M data from the N write-in data and the K extra data as decoding factors to retrieve the N write-in data. The higher the counter values, the lower the likelihood the corresponding bit is selected to be retrieved.

Abstract: A caching method provides a cashing mechanism between a logical addresses and a flash memory physical addresses. The cashing mechanism involves a search tree which contains a number of internal and external translation nodes. Each external translation node points to a link list of translation units, and each translation unit records a range of logical addresses and the corresponding range of physical addresses, in addition to a version value. By traversing the search tree to reach a translation unit, the physical address of a target logical address can be determined in an efficient manner. The version value of the translation unit can be used to determine the space taken up for storing the mapping of the logical and physical addresses should be released for reuse.

Abstract: An apparatus for random parity check and correction with BCH code is provided, including a BCH parity check code encoder, a channel, a BCH parity check code decoder, and a static RAM (SRAM). The BCH parity check code encoder uses the BCH encoding to encode the parity check code in writing to flash memory. The channel is connected to the BCH parity check code encoder to compute the parity check code and the message polynomial into receiving data. The BCH parity check code decoder is connected to the channel for inputting the receiving data and using BCH decoding to compute the eigen value and error address. The SRAM is connected to the BCH parity check code decoder so as to read error address from static RAM, correct the data and restores the corrected data to the SRAM. Therefore, this achieves the object of random parity check and correction with BCH code.

Abstract: An ultrawideband (UWB) frequency-tracking method and related device are provided. The method includes the following steps: (a) using an initial frequency seed to automatically track and compensate the clock signal of the USB peripheral device; (b) determining whether the automatic tracking and compensating of the clock signal is successful, for example, within a pre-defined duration; (c) if not successful in step (b), setting a new frequency seed; (d) setting the USB peripheral device off-line; and (e) reconnecting the USB peripheral device and using the new frequency seed to perform the tracking and compensating of the clock signal. The setting off-line step is to disable the pull-up resistor of the D+ signal or the pull-up resistor of the D? signal of the USB peripheral device so that the USB peripheral device becomes off-line.

Abstract: A portable storage device with encryption protection is provided, including a memory interface connected to a data access host for inputting decryption information from the data access host and for outputting to the data access host, an encryption promotion unit connected to the memory interface for recording the data protection status, at least an encryption control unit connected to the encryption promotion unit for identifying data encryption code or signal, and issuing enabling or disabling control signal, a protection gate unit connected to the encryption control unit and the memory interface for enabling or disabling the data transmission to the memory interface according to the control signal from encryption control unit, and at least a protected data region and invalid data region connected to protection gate unit for the protected data region to output data to data access host when protection gate unit being enabled, and for invalid data region to output invalid data to data access host when protecti

Abstract: A portable storage device with wireless encryption protection is provided, including wireless identification remote control, for transmitting identification signal and information or lock control signal through wireless transmission, a memory interface connected to a data access host, for inputting decryption information from the data access host and for outputting to data access host, a wireless protection gate unit connected to the memory interface for receiving the identification signal and information or lock control signal issued by the wireless identification remote control, and enabling or disabling the data transmission to the memory interface according to the identification result, and at least a protected data region connected to the wireless protection gate unit, for the protected data region to output data to data access host when the wireless protection gate unit being enabled, so that the portable storage device can achieve the objects of accurate and permanently effective wireless encryption.

Abstract: A bridge device for SATA-interfaced hosts is provided, including a pair of physical units, a pair of link units, a pair of transmission ports, and at least a bridge unit. Each physical unit provides the connection to a SATA-interfaced host. The link unit links the physical unit and the transmission port, and encodes and decodes the transmitted and received data. The transmission port controls the host-to-device connection, registers, and state of the SATA interface. The bridge unit connects between two transmission ports, and so that the two SATA-interfaced hosts can transmit and receive data. The bridge device of the present invention allows the SATA-interfaced hosts to transmit and receive data and signals at a high speed.

Abstract: A method for improving the lifespan of flash memory is provided. By defining and configuring a plurality of memory block counters, the method assigns a counter to each memory block to record the number of writes to the memory block. With configuring a threshold for the counter, the counter is compared to the threshold for each write to the memory block so as to determine the priority update, data erase, update and move. The counter is also synchronously erased, updated, and moved so that the number of the writes to the flash memory blocks can be controlled by the configuration. Hence, the object of prolonging lifespan and reliability of the flash memory access is achieved.

Abstract: A method and an apparatus for auto-tracking and compensating a clock frequency are disclosed. The method is suitable for being applied in USB controllers.

Abstract: An apparatus for fast access to flash memory is provided, including a flash memory and an access controller. A system data reserved region is configured in the flash memory to provide temporary storage for data and instruction used in the flash memory access. The access controller includes a flash memory control interface, a RAM, a RAM DMA unit, and an ECC unit. The flash memory control interface is connected to the flash memory. The DMA unit and the ECC unit are connected between the RAM and the flash memory control interface to provide direct access and error correction functions, as well as allowing, during the data access to the flash memory, the data and the system instruction of the system data reserved region in the flash memory to go through the flash memory control interface, the DMA unit and the ECC unit to load into the RAM for acting as an extended memory for the RAM to effect fast access to the flash memory and extending the RAM capacity.

Abstract: A multi-interface conversion device includes a USB-to-IDE interface bridging unit, an IDE-to-SATA interface bridging unit, an IDE switching unit, and a switching logic unit. The USB-to-IDE interface bridging unit provides USB to IDE bridging and conversion. The IDE-to-SATA interface bridging unit provides IDE to SATA interface conversion or IDE to eSATA interface conversion or SATA to eSATA interface conversion. The IDE-to-SATA interface bridging unit is connected to the USB-to-IDE interface bridging unit to transmit USB-to-IDE converted data to the IDE-to-SATA interface bridging unit to provide conversion between USB interface and SATA. The IDE switching unit is connected to the USB-to-IDE interface bridging unit and the IDE-to-SATA interface bridging unit for switching the output IDE interface and signal between the USB-to-IDE interface bridging unit and the IDE-to-SATA interface bridging unit.

Abstract: A method for parallelly processing data and ECC in the memory and associated apparatus are disclosed. The method includes the following steps: (1) reading the first data, and calculating the first syndrome based on the first data and the first ECC code, (2) correcting the first data according to the first syndrome, while reading the second data, and calculating the second syndrome based on the second data and the second ECC code, (3) and correcting the second data according to the second syndrome, while reading the third data and calculating the third syndrome based on the third data and the third ECC code.

Abstract: A method and an apparatus for dynamically configuring the redundant areas of a non-volatile memory is provided wherein each page of a memory is configured into a plurality of data areas and a plurality of redundant areas. The redundant areas interleave the data areas, or are arranged behind any data area. The system information and the status information is programmed into each data area of the page according to the original status information, so as to allow the flash drive to load a data area and an associated redundant area for each access operation with a smaller buffer.