Abstract: A purification apparatus and a method of purifying hot zone parts are provided. The purification apparatus is configured to remove impurities attached on at least one hot zone part. The purification apparatus includes a crystal high temperature furnace, an enclosed box disposed in the crystal high temperature furnace, an outer tube connected to the crystal high temperature furnace and the enclosed box, an inner tube disposed in the outer tube, and a gas inlet cover connected to the outer tube. The crystal high temperature furnace includes a furnace body, a furnace cover, and a thermal field module disposed in the furnace body. The gas inlet cover is configured to input a noble gas into the enclosed box through the inner tube, and the thermal field module is configured to heat the noble gas so that the impurities are heated and vaporized through the noble gas.

Abstract: Methods for etching a semiconductor structure and for conditioning a processing reactor in which a single semiconductor structure is treated are disclosed. An engineered polycrystalline silicon surface layer is deposited on a susceptor which supports the semiconductor structure. The polycrystalline silicon surface layer may be engineered by controlling the temperature at which the layer is deposited, by grooving the polycrystalline silicon surface layer or by controlling the thickness of the polycrystalline silicon surface layer.

Abstract: A wafer grinding parameter optimization method and an electronic device are provided. The method includes the following. A natural frequency of a grinding wheel spindle of wafer processing equipment is obtained, and a grinding stability lobe diagram is generated accordingly. A grinding speed is selected based on a speed range of the grinding wheel spindle. Multiple grinding parameter combinations are determined based on the grinding speed. Multiple grinding simulation result combinations corresponding to the grinding parameter combinations are generated. A specific grinding parameter combination is selected based on each of the grinding simulation result combinations, and the wafer processing equipment is set accordingly.

Abstract: Embodiments of the disclosure provide a method and device for providing a wire breakage warning. The method includes: obtaining a plurality of process values when a crystal ingot cutting machine uses a cutting wire to cut a crystal ingot; dividing the process values into N groups, and determining a statistical property of each of the groups; identifying outlier values in the process values based on the statistical property of each of the groups, or determining a statistical property variation corresponding to each of the groups based on the statistical property of each of the groups; and in response to determining that the outlier values in the process values meet a first warning condition, or the statistical property variation corresponding to each of the groups meets a second warning condition, providing a wire breakage warning associated with the cutting wire.

Abstract: An epitaxial structure includes a substrate, a first buffer layer, a second buffer layer, and a channel layer, wherein the first buffer layer is located on a top of the substrate and includes a first portion. The first portion includes a nitride, which is ternary and above, and an aluminum atom concentration of the first portion is less than or equal to 25 at %. The first portion has an element doping, wherein a doping concentration of the element doping of the first portion is greater than or equal to 1×1018 cm?3. The second buffer layer is located on a top of the first buffer layer. The second buffer layer is provided without aluminum and has an element doping. The channel layer is located on a top of the second buffer layer.

Abstract: Methods for preparing single crystal silicon substrates for epitaxial growth are disclosed. The methods may involve control of the (i) a growth velocity, v, and/or (ii) an axial temperature gradient, G, during the growth of an ingot segment such that v/G is less than a critical v/G and/or is less than a value of v/G that depends on the boron concentration of the ingot. Methods for preparing epitaxial wafers are also disclosed.

Abstract: Methods for preparing an ingot in an ingot puller apparatus are disclosed. Thermal simulations are performed with the length of the ingot puller apparatus side heater being varied in the thermal simulations. A side heater is selected based on the thermal simulations. An ingot puller apparatus having the selected side heater length is provided. A seed crystal is lowered into a melt within a crucible of the ingot puller apparatus and an ingot is withdrawn from the melt.

Abstract: A manufacturing method of a silicon carbide wafer includes the following. A raw material containing carbon and silicon and a seed located above the raw material are provided in a reactor. A nitrogen content in the reactor is reduced, which includes the following. An argon gas is passed into the reactor, where a flow rate of passing the argon gas into the reactor is 1,000 sccm to 5,000 sccm, and a time of passing the argon gas into the reactor is 2 hours to 48 hours. The reactor and the raw material are heated to form a silicon carbide material on the seed. The reactor and the raw material are cooled to obtain a silicon carbide ingot. The silicon carbide ingot is cut to obtain a plurality of silicon carbide wafers. A semiconductor structure is also provided.

Abstract: Methods for preparing single crystal silicon substrates for epitaxial growth are disclosed. The methods may involve control of the (i) a growth velocity, v, and/or (ii) an axial temperature gradient, G, during the growth of an ingot segment such that v/G is less than a critical v/G and/or is less than a value of v/G that depends on the boron concentration of the ingot. Methods for preparing epitaxial wafers are also disclosed.

Abstract: A crystal growth doping apparatus and a crystal growth doping method are provided. The crystal growth doping apparatus includes a crystal growth furnace and a doping device that includes a feeding tube inserted to the furnace body along an oblique insertion direction, and a storage cover and a gate tube that are disposed in the feeding tube. The feeding tube extends from an outer surface thereof to form a placement opening, and the placement opening is recessed from an edge thereof to form an upper recessed portion and a lower recessed portion along the oblique insertion direction. The storage cover includes a storage tank and a handle. When the storage cover is disposed in the gate tube body, the gate tube body is configured to isolate an inner space of the feeding tube from the placement opening.

Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a silicon nitride layer deposited by plasma deposition.

Abstract: Disclosed are a signal processing method and an abnormal sound detection system. First, a neural network model is trained, including: (a) randomly selecting a plurality of sample signals from a training database to obtain a combined signal, wherein the training database includes the first sample set belonging to the first classification label and the second sample set belonging to the second classification label, and the number of selected sample signals conforms to the preset number; repeating the said step to obtain a plurality of combined signals and using the combined signals to train the neural network model. Then, a sound signal received from a sound receiving apparatus is inputted to the trained neural network model to output a probability value, and a corresponding notification signal is outputted based on the probability value.

Abstract: Crystal pulling systems having a fluid-cooled exhaust tube are disclosed. The fluid-cooled exhaust tube extends through the reactor housing and into the reaction chamber. In some embodiments, the exhaust tube extends through the bottom of the crystal puller housing and through a bottom heat shield within the ingot puller housing.

Abstract: A wafer processing system and a rework method thereof are provided. An image capture device captures an image of a wafer to generate a captured image. A control device detects a defect pattern in the captured image, calculates a target removal thickness according to distribution of contrast values of the defect pattern, and controls a processing device to perform processing on the wafer according to the target removal thickness.

Abstract: A method for growing a single crystal silicon ingot by the Czochralski method having reduced deviation in diameter is disclosed.

Abstract: A silicon carbide crystal includes a seed layer, a bulk layer and a stress buffering structure formed between the seed layer and the bulk layer. The seed layer, the bulk layer and the stress buffering structure are each formed with a dopant that cycles between high and low dopant concentration. The stress buffering structure includes a plurality of stacked buffer layers and a transition layer over the buffer layers. The buffer layer closest to the seed layer has the same variation trend of the dopant concentration as the buffer layer closest to the transition layer, and the dopant concentration of the transition layer is equal to the dopant concentration of the seed layer.

Abstract: A semiconductor substrate includes a high-resistivity silicon carbide layer and a gallium nitride epitaxial layer. The gallium nitride epitaxial layer is formed on a surface, a thickness of the gallium nitride epitaxial layer is less than 2 ?m, and a full width at half maximum (FWHM) of an X-ray diffraction analysis (002) plane is less than 100 arcsec. The thickness of the high-resistivity silicon carbide layer ranges from 20 ?m to 50 ?m. The surface of the high-resistivity silicon carbide layer has an angle ranging from 0° to +/?8° with respect to a (0001) plane. The micropipe density (MPD) of the high-resistivity silicon carbide layer is less than 0.5 ea/cm2, the basal plane dislocation (BPD) of the high-resistivity silicon carbide layer is less than 10 ea/cm2, and the threading screw dislocation (TSD) of the high-resistivity silicon carbide layer is less than 500 ea/cm2.

Abstract: A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.

Abstract: A method for producing a silicon ingot by the horizontal magnetic field Czochralski method includes rotating a crucible containing a silicon melt, applying a horizontal magnetic field to the crucible, contacting the silicon melt with a seed crystal, and withdrawing the seed crystal from the silicon melt while rotating the crucible to form a silicon ingot. The crucible has a wettable surface with a cristobalite layer formed thereon.

Abstract: Methods for etching a semiconductor structure and for conditioning a processing reactor in which a single semiconductor structure is treated are disclosed. An engineered polycrystalline silicon surface layer is deposited on a susceptor which supports the semiconductor structure. The polycrystalline silicon surface layer may be engineered by controlling the temperature at which the layer is deposited, by grooving the polycrystalline silicon surface layer or by controlling the thickness of the polycrystalline silicon surface layer.