Abstract: A heterostructure, includes: a substrate; and a buffer layer that includes a plurality of layers having a composition AlxInyGa1-x-yN, where x?1 and y?0; wherein the buffer layer has a first region that includes at least two layers, a second region that includes at least two layers, and a third region that includes at least two layers.

Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.

Abstract: A heterostructure, includes: a substrate; and a buffer layer that includes a plurality of layers having a composition AlxInyGa1-x-yN, where x?1 and y?0; wherein the buffer layer has a first region that includes at least two layers, a second region that includes at least two layers, and a third region that includes at least two layers.

Abstract: A semiconductor structure, including a substrate, a first nitride layer, a polarity inversion layer, a second nitride layer, and a third nitride layer, is provided. The first nitride layer is located on the substrate. The polarity inversion layer is located on a surface of the first nitride layer to convert a non-metallic polarity surface of the first nitride layer into a metallic polarity surface of the polarity inversion layer. The second nitride layer is located on the polarity inversion layer. The third nitride layer is located on the second nitride layer. The substrate, the first nitride layer, the polarity inversion layer, and the second nitride layer include iron element.

Abstract: An ingot evaluation method and a detecting apparatus are provided. Defect information of a wafer is obtained from an ingot. The defect information includes a position of at least one defect identified by optical detection. A center-of-gravity position of the defect is determined according to the defect information. Uniformity of the defect is evaluated according to the center-of-gravity position. The uniformity is related to quality of a processed wafer.

Abstract: A method of manufacturing an epitaxy substrate is provided. A handle substrate is provided. A beveling treatment is performed on an edge of a device substrate such that a bevel is formed at the edge of the device substrate, wherein a thickness of the device substrate is greater than 100 ?m and less than 200 ?m. An ion implantation process is performed on a first surface of the device substrate to form an implantation region within the first surface. A second surface of the device substrate is bonded to the handle substrate for forming the epitaxy substrate, wherein a bonding angle greater than 90° is provided between the bevel of the device substrate and the handle substrate, and a projection length of the bevel toward the handle substrate is between 600 ?m and 800 ?m.

Abstract: A method for growing a single crystal silicon ingot by the continuous Czochralski method is disclosed. The melt depth and thermal conditions are constant during growth because the silicon melt is continuously replenished as it is consumed, and the crucible location is fixed. The critical v/G is determined by the hot zone configuration, and the continuous replenishment of silicon to the melt during growth enables growth of the ingot at a constant pull rate consistent with the critical v/G during growth of a substantial portion of the main body of the ingot. The continuous replenishment of silicon is accompanied by periodic or continuous nitrogen addition to the melt to result in a nitrogen doped ingot.

Abstract: A method for growing a single crystal silicon ingot by the continuous Czochralski method is disclosed. The melt depth and thermal conditions are constant during growth because the silicon melt is continuously replenished as it is consumed, and the crucible location is fixed. The critical v/G is determined by the hot zone configuration, and the continuous replenishment of silicon to the melt during growth enables growth of the ingot at a constant pull rate consistent with the critical v/G during growth of a substantial portion of the main body of the ingot. The continuous replenishment of silicon is accompanied by periodic or continuous nitrogen addition to the melt to result in a nitrogen doped ingot.

Abstract: A liner assembly for a substrate processing system includes a first liner and a second liner. The first liner includes an annular body and an outer peripheral surface including a first fluid guide. The first fluid guide is curved about a circumferential line extending around the first liner. The second liner includes an annular body, an outer rim, an inner rim, a second fluid guide extending between the outer rim and the inner rim, and a plurality of partition walls extending outwardly from the second fluid guide. The second fluid guide is curved about the circumferential line when the first and second liners are positioned within the processing system.

Abstract: A method for producing a silicon ingot includes withdrawing a seed crystal from a melt that includes melted silicon in a crucible that is enclosed in a vacuum chamber containing a cusped magnetic field. At least one process parameter is regulated in at least two stages, including a first stage corresponding to formation of the silicon ingot up to an intermediate ingot length, and a second stage corresponding to formation of the silicon ingot from the intermediate ingot length to the total ingot length. During the second stage process parameter regulation may include reducing a crystal rotation rate, reducing a crucible rotation rate, and/or increasing a magnetic field strength relative to the first stage.

Abstract: A method for producing Si ingot single crystal including a Si ingot single crystal growing step, a temperature gradient controlling step and a continuous growing step is provided. In the growing step, the Si ingot single crystal is grown in silicon melt in crucible, and the growing step includes providing a low-temperature region in the Si melt and providing a silicon seed to contact the melt surface of the silicon melt to start crystal growth, and silicon single crystal grows along the melt surface of the silicon melt and toward the inside of the silicon melt. In the temperature gradient controlling step, the under-surface temperature gradient of the silicon single crystal is G1, the above-surface temperature gradient of the silicon single crystal is G2, G1 and G2 satisfy: G2/G1<6. The step of controlling the temperature gradient of silicon single crystal is repeated to obtain the Si ingot single crystal.

Abstract: A method for preparing a single crystal silicon ingot and a wafer sliced therefrom are provided. The ingots and wafers comprise nitrogen at a concentration of at least about 1×1014 atoms/cm3 and/or germanium at a concentration of at least about 1×1019 atoms/cm3, interstitial oxygen at a concentration of less than about 6 ppma, and a resistivity of at least about 1000 ohm cm.

Abstract: A method for preparing a single crystal silicon ingot and a wafer sliced therefrom are provided. The ingots and wafers comprise nitrogen at a concentration of at least about 1×1014 atoms/cm3 and/or germanium at a concentration of at least about 1×1019 atoms/cm3, interstitial oxygen at a concentration of less than about 6 ppma, and a resistivity of at least about 1000 ohm cm.

Abstract: A semiconductor epitaxy structure includes a silicon carbide substrate, a nucleation layer, a gallium nitride buffer layer, and a stacked structure. The nucleation layer is formed on the silicon carbide substrate, the gallium nitride buffer layer is disposed on the nucleation layer, and the stacked structure is formed between the nucleation layer and the gallium nitride buffer layer. The stacked structure includes: a plurality of silicon nitride (SiNx) layers and a plurality of aluminum gallium nitride (AlxGa1-xN) layers alternately stacked, wherein the first layer of the plurality of silicon nitride layers is in direct contact with the nucleation layer.

Abstract: A method for calculating an object pick-and-place sequence and an electronic apparatus for automatic storage pick-and-place are provided. When a warehousing operation is to be performed, the following steps are performed. A weight of an object to be stocked that is to be put on a shelf is obtained. The weight is substituted into a plurality of coordinate positions corresponding to a plurality of unused grid positions respectively, so as to calculate a plurality of estimated center of gravity positions. Whether the estimated center of gravity positions are located within a balance standard area is determined so as to sieve out a plurality of candidate grid positions from these unused grid positions. One of the candidate grid positions is selected as a recommended position of the object to be stocked.

Abstract: Provided is a wafer jig including a bottom wall and a ring-shaped side wall. The bottom wall has a supporting surface. The ring-shaped side wall is connected to a periphery of the bottom wall. The ring-shaped side wall includes at least two step portions. The two step portions include a first step portion and a second step portion. The first step portion is connected between the supporting surface and the second step portion, and the first step portion protrudes along a direction toward a center of the bottom wall. The ring-shaped side wall surrounds the center. In addition, a wafer structure and a wafer processing method are also provided.

Abstract: A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.

Abstract: A preheat ring (126) for use in a chemical vapor deposition system includes a first portion and a second portion selectively coupled to the first portion such that the first and second portions combine to form an opening configured to receive a susceptor therein. Each of the first and second portions is independently moveable with respect to each other.

Abstract: A method for identifying a wafer is provided, which includes the following steps. A marked frame is obtained from a wafer inspection picture. A gray scale index corresponding to the marked frame is calculated based on a gray scale value corresponding to each of multiple pixels included in the marked frame. The gray scale index indicates a proportion of pixels whose gray scale values are greater than a specified value. Whether a trace pattern in the marked frame is a scratch or a grain boundary is determined based on the gray scale index.

Abstract: The disclosure provides a silicon carbide seed crystal and a method of manufacturing a silicon carbide ingot. The silicon carbide seed crystal has a silicon surface and a carbon surface opposite to the silicon surface. A difference D between a basal plane dislocation density BPD1 of the silicon surface and a basal plane dislocation density BPD2 of the carbon surface satisfies the following formula (1), a local thickness variation (LTV) of the silicon carbide seed crystal is 2.5 ?m or less, and a stacking fault (SF) density of the silicon carbide seed crystal is 10 EA/cm2 or less: D=(BPD1?BPD2)/BPD1?25%??(1).