Abstract: A circuit structure includes an enhancement mode transistor and a turn-off slew rate controller for automatically adding drain-source capacitance to the transistor when the transistor is transitioning to an off state. The added drain-source capacitance slows the turn-off slew rate (dV/dt_off) of the transistor without also increasing the turn-off energy loss (E_off). The slew rate controller can include: sensors connected to the drain region for sensing both the drain voltage and the slew rate, respectively; a logic circuit for generating and outputting an enable signal based on output voltages from the sensors; and a capacitance adder for adding to the drain-source capacitance only when the logic value of the enable signal indicates that the drain voltage is at or above a predetermined positive drain voltage level and the slew rate is positive.

Abstract: A structure provides a defect sensor for a cavity in an integrated circuit (IC). The structure includes a cavity defined in a substrate. A boundary is located where the cavity meets with a cavity-free area of the substrate. A metal line is arranged in a serpentine path in both a vertical and a horizontal direction and crosses the boundary. A controller may be provided that is configured to, in response to a change in an electrical characteristic of a signal through the metal line, generate an indication of the presence of a defect and/or change operation of at least one component of the IC. The structure may find application relative to a photonics integrated circuit (PIC) structure including an optical waveguide with a cavity under the optical waveguide.

Abstract: Structures including multiple semiconductor devices and methods of forming same. The structure comprises a first device structure including a first well and a second well in a semiconductor substrate, a second device structure including a doped region in the semiconductor substrate, and a first high-resistivity region in the semiconductor substrate. The first well has a first conductivity type, the second well has a second conductivity type opposite to the first conductivity type, and the first well adjoins the second well to define a p-n junction. The doped region of the second device structure has the first conductivity type or the second conductivity type. The high-resistivity region has a higher electrical resistivity than the semiconductor substrate, and the high-resistivity region is positioned between the first device structure and the second device structure.

Abstract: A photonic integrated circuit (PIC) structure includes a substrate, and a cavity defined in the substrate, the cavity including a shoulder at a side of the cavity. A plurality of z-stop supports for an optical device are also included. Each z-stop support of the plurality of z-stop supports is on a support portion of the shoulder. A wire extends over the side of the cavity and between at least two z-stop supports of the plurality of z-stop supports. An optical device is positioned on the plurality of z-stop supports in the cavity and electrically coupled to the wire. Electrical connections between z-stop supports allows larger sized electrical connections to the optical device to mitigate electromigration issues, and increased options for electrical connections.

Abstract: An IC structure that includes a trench isolation (TI) in a substrate having three portions of different dielectric materials. The portions may also have different widths. The TI may include a lower portion including a first dielectric material and having a first width, a middle portion including the first dielectric material and an outer second dielectric material, and an upper portion including a third dielectric material and having a second width greater than the first width. The first, second and third dielectric materials are different.

Abstract: Structures for an optical coupler and methods of forming an optical coupler. The structure comprises a first waveguide core including a first tapered section, a second waveguide core including a second tapered section overlapped with the first tapered section, and an active layer including a third tapered section overlapped with the second tapered section. The first waveguide core comprises a first passive material, the second waveguide core comprises a second passive material, and the active layer comprises an active material.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with a metal field plate extension and methods of manufacture. The structure includes: a gate structure over a semiconductor substrate; a drift region under the gate structure; a source region adjacent to the gate structure; a drain region in the drift region; a isolation structure within the drift region; and a contact extending from the source region and into the isolation structure within the drift region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to cell layouts in semiconductor structures and methods of manufacture. A structure includes: a plurality of abutting cells each of which include transistors with gate structures having diffusion regions; a contact spanning across abutting cells of the plurality of abutting cells and contacting to the diffusion regions of separate cells of the abutting cells; and a continuous active region spanning across the plurality of abutting cells, wherein the continuous active region includes a drain-source abutment with L-shape construct, a source-source abutment with U-shape construct, and a drain-drain abutment with a filler cell located between a drain-drain abutment.

Abstract: A device includes a buried oxide layer disposed on a substrate, a first region disposed on the buried oxide layer and a first ring region disposed in the first region. The first ring region includes a portion of a guardring. The device further includes a first terminal region disposed in the first ring region, a second ring region disposed in the first region and a second terminal region disposed in the second ring region. The first terminal region is connected to an anode and the second terminal region is connected to a cathode. The first region has a graded doping concentration. The first region, the second ring region and the second terminal region have a first conductivity type, and the first ring region and the first terminal region have a second conductivity type. The first conductivity type is different from the second conductivity type.

Abstract: A semiconductor device includes a dielectric layer over a back end of line (BEOL) metal layer, a metallic resistive layer over the dielectric layer, a resistor comprising a metallic resistive film that is a first portion of the metallic resistive layer, and a metal-insulator-metal (MIM) capacitor. The insulator of the MIM capacitor comprises at least two layers including a first layer that is a second portion of the metallic resistive layer and a second layer that is the dielectric layer.

Abstract: A structure includes a level shifter, first and second variable voltage generators, and a programmable voltage generator. The level shifter includes low and high supply voltage nodes and two parallel branches, including multiple transistors, connected between the nodes. The programmable voltage generator generates and applies a high supply voltage (VH) to the high supply voltage node. VH is programmable to one of multiple possible VH levels. Based on the voltage level of VH, the first variable voltage generator generates and applies a low supply voltage (VL) to the low supply voltage node and the second variable voltage generator generates and applies a gate bias voltage (VGB) to gates of some transistors. By tracking VH and adjusting VL and VGB based on thereon, the voltage level shifter operates within the SOA at high VHs, remains operable at low VHs, and maintains operating speed at mid-level VHs.

Abstract: According to various embodiments, there may be provided an interposer. The interposer including: a substrate; a dielectric layer disposed on the substrate; a via disposed entirely within the dielectric layer; a resistive film layer disposed to line the via; a metal interconnect disposed in the resistive layer lined via; and a plurality of metal lines disposed in the dielectric layer, the plurality of metal lines including a first metal line connected to the metal interconnect, a second metal line connected to the resistive film layer at a first point, and a third metal line connected to the resistive film layer at a second point.

Abstract: Disclosed is a semiconductor structure with a photodiode including: a well region with a first-type conductivity in a substrate, a trench in the well region, and multiple conformal semiconductor layers in the trench. The semiconductor layers include a first semiconductor layer, which is, for example, an intrinsic semiconductor layer and lines the trench, and a second semiconductor layer, which has a second-type conductivity and which is on the first semiconductor layer within (but not filling) the trench and which also extends outside the trench onto a dielectric layer. An additional dielectric layer extends over and caps a cavity that is at least partially within the trench such that surfaces of the second semiconductor layer are exposed within the cavity. Fluid inlet/outlet ports extend to the cavity and contacts extend to the well region and to the second semiconductor layer. Also disclosed are methods for forming and using the semiconductor structure.

Abstract: A memory device may be provided, including a first planar electrode, a second planar electrode, and a switching element arranged between the first planar electrode and the second planar electrode to where a first side of the switching element is arranged over the first planar electrode and where a second side of the switching element is arranged under the second planar electrode. The switching element is thicker at the first side than the second side, and the switching element is configured to provide a conductive filament formation region.

Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure comprises a first terminal including a first raised semiconductor layer, a second terminal including a second raised semiconductor layer, and a base layer positioned in a lateral direction between the first raised semiconductor layer of the first terminal and the second raised semiconductor layer of the second terminal. The structure further comprises a modulator including a semiconductor layer in direct contact with the base layer. The base layer has a first conductivity type, and the semiconductor layer has a second conductivity type opposite to the first conductivity type.

Abstract: Structures and methods implement an enlarged multilayer nitride waveguide. The structure may include an inter-level dielectric (ILD) layer over a substrate. A first enlarged multilayer nitride waveguide is positioned in the ILD layer in a region of the substrate. A second multilayer nitride waveguide may also be provided in the ILD layer. A lower cladding layer defines a lower surface of the nitride waveguide(s). The lower cladding layer has a lower refractive index than the nitride waveguide(s). Additional lower refractive index cladding layers can be provided on the upper surface and/or sidewalls of the nitride waveguide(s). The enlarged nitride waveguide may be implemented with other conventional silicon and nitride waveguides.

Abstract: Disclosed are embodiments of a photonic structure with at least one tapered coupler positioned laterally adjacent and along the length of a sidewall of a layer, such as a light absorption layer (LAL), of a photodetector to facilitate mode matching. Some embodiments include a vertically oriented photodetector, which is on an insulator layer and has an LAL stacked between bottom and top semiconductor layers, and a coupler, which is on the insulator layer positioned laterally adjacent to the photodetector and has stacked cores with one of the cores being at the same level as the LAL. Other embodiments include a horizontally oriented photodetector, which is on an insulator layer and has an LAL on a recessed section of a bottom semiconductor layer between side sections, and coupler(s), which is/are above side section(s) of the bottom semiconductor layer and, thus, positioned laterally adjacent to one or both sides of the LAL.

Abstract: An integrated circuit (IC) structure includes a transistor in a device layer over a substrate, the transistor including a gate; and a plurality of interconnect layers over the device layer, the plurality of interconnect layers including a last metal layer. A process-induced damage (PID) protection structure includes a conductor coupling the gate to a well in the substrate but includes an open fuse element therein. A first metal interconnect extends from a first terminal of the open fuse element to a first pad in the last metal layer, and a second metal interconnect extending from a second terminal of the open fuse element to a second pad in the last metal layer. The fuse element is closed during fabrication, and the metal interconnects allow opening of the fuse element to deactivate the PID protection structure after fabrication.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with a stepped emitter and methods of manufacture. The structure includes: a collector; a base over the collector; and an emitter over the base, the emitter comprising at least one stepped feature over the base.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heat dissipating structures and methods of manufacture. The structure includes: a thin film resistor within a back end of the line structure; and a heat dissipating structure below the thin film resistor, the heat dissipating structure includes a top plate with a slotted configuration and being within the back end of the line structure.