Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion cut for gate structures and methods of manufacture. The structure includes: a plurality of fin structures; a plurality of gate structures extending over the plurality of fin structures; a plurality of diffusion regions adjacent to the each of the plurality of gate structures; a single diffusion break between the diffusion regions of the adjacent gate structures; and a liner separating the single diffusion break from the diffusion regions.

Abstract: The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to high electron mobility transistor (HEMT) devices having a silicided polysilicon layer. The present disclosure may provide an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region, the gate being laterally between the source and drain electrodes, a polysilicon layer above the substrate, and a silicide layer on the polysilicon layer. The active region includes at least two material layers with different band gaps. The polysilicon layer may be configured as an electronic fuse, a resistor, or a diode.

Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a substrate having a well, a first terminal including a first raised semiconductor layer, a second terminal including a second raised semiconductor layer, and a base layer positioned in a lateral direction between the first raised semiconductor layer of the first terminal and the second raised semiconductor layer of the second terminal. The base layer has an overlapping arrangement with the well. The structure further includes a dielectric layer positioned in a vertical direction between the first terminal and the substrate, the second terminal and the substrate, and the base layer and the substrate.

Abstract: Embodiments of the present disclosure provide a level-sensitive register unit, including: a data latch for receiving data; a flip-flop including a first latch and a second latch, wherein an output of the data latch is coupled to an input of the first latch of the flip-flop; a first clock signal coupled to the data latch; and a second clock signal, wherein the second latch of the flip-flop is clocked by the second clock signal, and wherein the first latch of the flip-flop is clocked by an inverse of the second clock signal.

Abstract: Embodiments of the disclosure provide a bipolar transistor structure having a base with a varying horizontal width and methods to form the same. The bipolar transistor structure includes a first emitter/collector (E/C) layer on an insulator layer. A base layer is over the insulator layer. A spacer between the first E/C layer and the base layer. The base layer includes a lower base region, and the spacer is adjacent to the lower base region and the first E/C layer. An upper base region is on the lower base region and the spacer. A horizontal width of the upper base region is larger than a horizontal width of the lower base region.

Abstract: Disclosed are embodiments of a transistor (e.g., a III-V high electron mobility transistor (HEMT), a III-V metal-insulator-semiconductor HEMT (MISHEMT), or the like) that has multiple self-aligned terminals. The self-aligned terminals include a self-aligned gate, a self-aligned source terminal and, optionally, a self-aligned drain terminal. By forming self-aligned terminals during processing, the separation distances between the terminals (e.g., between the gate and source terminal and, optionally, between the gate and drain terminal) can be reduced in order to reduce device size and to improve performance (e.g., to reduce on resistance and increase switching speeds). Also disclosed herein are method embodiments for forming such a transistor.

Abstract: Disclosed are a motion-sensitive field effect transistor (MSFET), a motion detection system, and a method. The MSFET includes a gate structure with a reservoir containing conductive fluid and gate electrode(s). Given position(s) of the gate electrode(s) and a fill level of the fluid within the reservoir, contact between the gate electrode(s) and the fluid depends upon the orientation the MSFET channel region relative to the top surface of the conductive fluid and the orientation of the MSFET channel region relative to the top surface of the conductive fluid depends upon position in space and/or movement of the MSFET and, particularly, position in space and/or movement of the chip on which the MSFET is formed. An electrical property of the MSFET in response to specific bias conditions varies depending on whether or not or to what extent the gate electrode(s) contact the fluid and is, thus, measurable for sensing chip motion.

Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a first terminal having a first raised semiconductor layer on a semiconductor substrate, a second terminal having a second raised semiconductor layer on the semiconductor substrate, and an intrinsic base on the semiconductor substrate. The intrinsic base is positioned in a lateral direction between the first raised semiconductor layer of the first terminal and the second raised semiconductor layer of the second terminal. The intrinsic base includes a portion containing silicon-germanium with a germanium concentration that is graded in the lateral direction.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor and methods of manufacture. The structure includes: a collector region in a semiconductor substrate; a base region adjacent to the collector region; and an emitter extending above the base region and comprising semiconductor material and a hardmask surrounding a lower portion of the semiconductor material.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The method includes: forming a first gate structure and a second gate structure with gate materials; etching the gate materials within the second gate structure to form a trench; and depositing a conductive material within the trench so that the second gate structure has a metal composition different than the first gate structure.

Abstract: A monitoring system and method are provided for determining at least one property of an integrated circuit (IC) comprising a multi-layer structure formed by at least a layer on top of an underlayer. The monitoring system receives measured data comprising data indicative of optical measurements performed on the IC, data indicative of x-ray photoelectron spectroscopy (XPS) measurements performed on the IC and data indicative of x-ray fluorescence spectroscopy (XRF) measurements performed on the IC. An optical data analyzer module analyzes the data indicative of the optical measurements and generates geometrical data indicative of one or more geometrical parameters of the multi-layer structure formed by at least the layer on top of the underlayer.

Abstract: Structures for a semiconductor device that include dielectric isolation and methods of forming a structure for a semiconductor device that includes dielectric isolation. A semiconductor body includes a cavity, first and second gate structures extending over the semiconductor body, and a semiconductor layer including first and second sections on the semiconductor body. The first section of the semiconductor layer is laterally positioned between the cavity and the first gate structure, and the second section on the semiconductor layer is laterally positioned between the cavity and the second gate structure. An isolation structure is laterally positioned between the first and second sections of the semiconductor layer. The isolation structure includes a dielectric layer and a sidewall spacer having first and second sections. The dielectric layer includes a first portion in the cavity and a second portion between the first and second sections of the sidewall spacer.

Abstract: Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming a structure for a laterally-diffused metal-oxide-semiconductor device. The structure includes a drift well in a semiconductor substrate, source and drain regions in the semiconductor substrate, a gate dielectric layer on the semiconductor substrate, and a buffer dielectric layer on the semiconductor substrate over the drift well. The buffer dielectric layer includes a first side edge adjacent to the drain region, a second side edge adjacent to the gate dielectric layer, a first section extending from the second side edge to the first side edge, and a plurality of second sections extending from the second side edge toward the first side edge. The first section has a first thickness, and the second sections have a second thickness less than the first thickness. A gate electrode includes respective portions that overlap with the buffer dielectric layer and with the gate dielectric layer.

Abstract: Embodiments of the disclosure provide a lateral bipolar transistor with a base layer of varying horizontal thickness, and related methods to form the same. A lateral bipolar transistor may include an emitter/collector (E/C) layer on a semiconductor layer. A first base layer is on the semiconductor layer and horizontally adjacent the E/C layer. The first base layer has a lower portion having a first horizontal width from the E/C layer. The first base layer also has an upper portion on the lower portion, with a second horizontal width from the E/C layer greater than the first horizontal width. A second base layer is on the first base layer and adjacent a spacer. The upper portion of the first base layer separates a lower surface of the second base layer from the E/C layer.

Abstract: Disclosed is a structure for implementing a Physically Unclonable Function (PUF)-based random number generator and a method for forming the structure. The structure includes same-type, same-design devices in a semiconductor layer. While values of a performance parameter exhibited by some devices (i.e., first devices) are within a range established based on the design, values of the same performance parameter exhibited by other devices (i.e., second devices) is outside that range. A random distribution of the first and second devices is achieved by including randomly patterned dopant implant regions in the semiconductor layer. Each first device is separated from the dopant implant regions such that its performance parameter value is within the range and each second device has a junction with dopant implant region(s) such that its performance parameter value is outside the range or vice versa. A random number generator can be operably connected to the devices to generate a PUF-based random number.

Abstract: A chip module, including a radio frequency integrated circuit (RFIC) chip and a package, and a method and system for designing the module. Chip and package design are performed so the RF front end (FE) is split between chip and package. The chip includes an amplifier with a first differential port and the package includes a passive device and matching network with a second differential port connected to the first differential port. The second differential port is power matched to the first differential port using complex power matching based on port voltage reflection coefficients in order to achieve improved performance (i.e., a peak power transfer across a bandwidth as opposed to at only one frequency). The power matching process can result in a chip power requirement reduction that allows for device size scaling. Thus, designing the chip and designing the package is iteratively repeated in a chip-package co-optimization process.

Abstract: Disclosed is a memory structure that includes wordlines (WL) and cell supply lines (CSL) positioned between and parallel to voltage boost lines (VBLs). The VBLs enable capacitive coupling-based voltage boosting of the adjacent WL and/or CSL depending on whether a read or write assist is required. During a read operation, all VBLs for a selected row can be charged to create coupling capacitances with the WL and with the CSL and thereby boost both the wordline voltage (Vwl) and the cell supply voltage (Vcs) for a read assist. During a write operation, one VBL adjacent to the WL for a selected row can be charged to create a coupling capacitance with the WL only and thereby boost the Vwl for a write assist. The coupling capacitances created by charging VBLs in the structure is self-adjusting in that as the length of the rows increase so do the potential coupling capacitances.

Abstract: The disclosure provides an integrated circuit (IC) structure with fluorescent materials, and related methods. An IC structure according to the disclosure may include a layer of fluorescent material on an IC component. The layer of fluorescent material defines a portion of an identification marker for the IC structure.

Abstract: A transistor may include a buffer layer, source and drain contacts on the buffer layer, a barrier layer on the buffer layer, a conductive member on the barrier layer, a dielectric stack, and a gate metal. The barrier layer may be between the source and drain contacts. The conductive member may include a p-doped III-V compound. The dielectric stack may be on the barrier layer and on the conductive member. The dielectric stack may include a first dielectric layer and a second dielectric layer on the first dielectric layer. First and second trenches may extend through the dielectric stack to the conductive member and to the first dielectric layer, respectively. The gate metal may be on the dielectric stack, and may contact the conductive member through the first trench and may contact the first dielectric layer through the second trench.

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a substrate having an active region, a source region, a drain region, and a floating gate. The source region and the drain region may be arranged in the active region, the drain region may be arranged adjacent to the source region. The source region and the drain region may define a channel region therebetween. The floating gate may be arranged over the active region, and may include a first section over the channel region, a plurality of second sections over the drain region, and a connecting section arranged between the first section and the plurality of second sections.