Patents Assigned to GLOBALFOUNDRIES Inc.
  • Publication number: 20200168504
    Abstract: Methods comprising forming a cobalt formation on an active feature of a semiconductor device, wherein the semiconductor device comprises an inactive feature above the cobalt formation; forming a cap on the cobalt formation; removing at least a portion of the inactive feature, wherein the cobalt formation is substantially not removed; forming a dielectric material above the cap; and forming a first contact to the cobalt formation. Systems configured to implement the methods. Semiconductor devices produced by the methods.
    Type: Application
    Filed: January 31, 2020
    Publication date: May 28, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Vimal Kamineni, Ruilong Xie, Mark Raymond
  • Publication number: 20200167127
    Abstract: Disclosed is a parallel prefix adder structure with a carry bit generation circuit that generates primary carry bits for only some bit pairs and a sum circuit with ripple carry adders that use these primary carry bits to generate secondary carry bits and sum bits for a final sum. The carry bit generation circuit has different sections, which process different sequential sets of bit pairs and which have different sparsity configurations. As a result, generation of the primary carry bits is non-uniform. That is, in the different sections the primary carry bits are generated at different carry bit-to-bit pair ratios (e.g., the carry bit-to-bit pair ratios for the different sections can be 1:2, 1:4, and 1:2, respectively). For optimal performance, the specific bit pairs for which these primary carry bits are generated varies depending upon whether the maximum operand size is an odd number of bits or an even number.
    Type: Application
    Filed: November 27, 2018
    Publication date: May 28, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ranjan B. Lokappa, Igor Arsovski
  • Patent number: 10665281
    Abstract: A device is disclosed including a first resistive storage element, a first access transistor having a first terminal coupled to the first resistive storage element at a first node, a second resistive storage element, a second access transistor having a first terminal coupled to the second resistive storage element at a second node, and a write assist transistor having a first terminal coupled to the first node and a second terminal coupled to the second node.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: May 26, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ajey Poovannummoottil Jacob, Amogh Agrawal, Bipul C. Paul
  • Patent number: 10665667
    Abstract: The present disclosure relates to a semiconductor device, and more particularly, to a junctionless/accumulation mode transistor with dynamic control and method of manufacturing. The circuit includes a channel region and a threshold voltage control on at least one side of the channel region, the threshold voltage control being configured to provide dynamic control of a voltage threshold, leakage current, and breakdown voltage of the circuit, wherein the threshold voltage control is a different dopant or material of a source region and a drain region of the circuit.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: May 26, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Anupam Dutta, John J. Ellis-Monaghan
  • Patent number: 10665586
    Abstract: A method of concurrently forming source/drain contacts (CAs) and gate contacts (CBs) and device are provided. Embodiments include forming metal gates (PC) and source/drain (S/D) regions over a substrate; forming an ILD over the PCs and S/D regions; forming a mask over the ILD; concurrently patterning the mask for formation of CAs adjacent a first portion of each PC and CBs over a second portion of the PCs; etching through the mask, forming trenches extending through the ILD down to a nitride capping layer formed over each PC and a trench silicide (TS) contact formed over each S/D region; selectively growing a metal capping layer over the TS contacts formed over the S/D regions; removing the nitride capping layer from the second portion of each PC; and metal filling the trenches, forming the CAs and CBs.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: May 26, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Cheng Chi
  • Patent number: 10665669
    Abstract: An IC structure according to the disclosure includes an insulative structure overlying a substrate and set of STIs. The insulative structure includes an isolation layer contacting an upper surface of the substrate, and a diffusion break region integral with and extending from the isolation layer, wherein the diffusion break region horizontally separates a pair of upper surfaces of the isolation layer. A pair of active semiconductor layers, each positioned on a respective one of the pair of upper surfaces of the isolation layer, are adjacent opposing sidewalls of the diffusion break region. The isolation layer electrically separates the pair of active semiconductor layers from the substrate, and the diffusion break region electrically separates the pair of active semiconductor layers from each other.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: May 26, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Julien Frougier
  • Patent number: 10665590
    Abstract: The present disclosure relates to integrated circuit (IC) structures and their method of manufacture. More particularly, the present disclosure relates to forming a semiconductor device having generally fork-shaped contacts around epitaxial regions to increase surface contact area and improve device performance. The integrated circuit (IC) structure of the present disclosure comprises a plurality of fins disposed on a semiconductor substrate, at least one epitaxial region laterally disposed on selected fins, and a contact material positioned over and surrounding the epitaxial region.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: May 26, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, William Taylor, Hui Zang
  • Patent number: 10664638
    Abstract: Measuring SRAM structures having FinFET transistors by obtaining, on a production semiconductor wafer, spectra of a SRAM production structure including FinFET fins and gates, identifying SRAM reference structure spectra corresponding to the spectra, the reference structure from measuring, on a reference semiconductor wafer, a reference structure including a layout of FinFET fins having gates, injecting, into an OCD model of the production structure, fin target parameter values, corresponding to the identified reference structure spectra, from measuring, on the reference wafer, a fin target including a layout of exposed FinFET fins lacking gates similar or identical to the reference structure layout, correspondence between the fin target parameter values and the reference structure spectra previously identified by ML, and determining measurement values for the FinFET gates of the production structure by fitting reference spectra associated with the production structure in the OCD model to the production struct
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: May 26, 2020
    Assignees: GLOBALFOUNDRIES INC., NOVA MEASURING INSTRUMENTS LTD.
    Inventors: Taher Kagalwala, Sridhar Mahendrakar, Matthew Sendelbach, Alok Vaid
  • Publication number: 20200159105
    Abstract: Methods pattern a sacrificial material on an etch mask into mandrels using optical mask lithography, form a conformal material and a fill material on the mandrels, and planarize the fill material to the level of the conformal material. Such methods pattern the fill material into first mask features using extreme ultraviolet (EUV) lithography. These methods partially remove the conformal material to leave the conformal material on the sidewalls of the mandrels as second mask features. Spaces between the first mask features and the second mask features define an etching pattern. The spacing distance of the mandrels is larger than the spacing distance of the second mask features. Such methods transfer the etching pattern into the etch mask material, and subsequently transfer the etching pattern into an underlying layer. Openings in the underlying layer are filled with a conductor to form wiring in the etching pattern.
    Type: Application
    Filed: November 15, 2018
    Publication date: May 21, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Jia Zeng, Guillaume Bouche, Lei Sun, Geng Han
  • Patent number: 10658494
    Abstract: Devices and methods of fabricating vertical nanowires on semiconductor devices are provided. One method includes: obtaining an intermediate semiconductor device having a substrate, a first insulator disposed above the substrate, a material layer over the first insulator, a second insulator above the material layer, and a first hardmask; etching a plurality of vertical trenches through the hardmask, the first and second insulators, and the material layer; growing, epitaxially, a set of silicon nanowires from a bottom surface of the plurality of vertical trenches; etching a first set of vertical trenches to expose the material layer; etching a second set of vertical trenches to the substrate; depositing an insulating spacer material on a set of sidewalls of the first and second set of vertical trenches; and forming contacts in the first and second set of vertical trenches.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: May 19, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Dominic J. Schepis, Alexander Reznicek
  • Patent number: 10658388
    Abstract: A method includes forming a first circuit element in and above a first semiconductor layer, the first semiconductor layer being formed on a first buried insulating layer, forming drain and source regions of the first circuit element at least partially in the first semiconductor layer, and forming a layer stack above the first circuit element, the layer stack including a conductive layer, a second buried insulating layer formed above the conductive layer, and a second semiconductor layer formed above the second buried insulating layer, wherein the conductive layer is electrically isolated from the drain and source regions.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: May 19, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Bartlomiej Pawlak
  • Patent number: 10658506
    Abstract: A fin cut last methodology for manufacturing a vertical FinFET includes forming a plurality of semiconductor fins over a substrate, forming shallow trench isolation between active fins and, following the formation of a functional gate of the active fins, using a selective etch to remove a sacrificial fin from within an isolation region. A further etching step can be used to remove a portion of the gate stack proximate to the sacrificial fin to create an isolation trench and a laterally-extending cavity within the isolation region that are back-filled with an isolation dielectric.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: May 19, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chanro Park, Kangguo Cheng
  • Patent number: 10658363
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cut inside a replacement metal gate trench to mitigate n-p proximity effects and methods of manufacture. The structure described herein includes: a first device; a second device, adjacent to the first device; a dielectric material, of the first device and the second device, including a cut within a trench between the first device and the second device; and a common gate electrode shared with the first device and the second device, the common gate electrode provided over the dielectric material and contacting underlying material within the cut.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: May 19, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Balaji Kannan, Ayse M. Ozbek, Tao Chu, Bala Haran, Vishal Chhabra, Katsunori Onishi, Guowei Xu
  • Patent number: 10658390
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to virtual drains for decreased harmonic generation in fully depleted SOI (FDSOI) RF switches and methods of manufacture. The structure includes one or more active devices on a semiconductor on insulator material which is on top of a substrate; and a virtual drain region composed of a well region within the substrate and spaced apart from an active region of the one or more devices, the virtual drain region configured to be biased to collect electrons which would accumulate in the substrate.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: May 19, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Edward J. Nowak, Richard F. Taylor, Tamilmani Ethirajan
  • Patent number: 10658294
    Abstract: In an exemplary structure, a first conductor connects a power source to integrated circuit devices. The first conductor includes a first axis defining a first side and a second side. A second conductor, perpendicular to the first conductor, is connected to the first conductor by first vias. A third conductor, parallel to the first conductor, is connected to the second conductor by second vias. The third conductor includes a second axis defining a third side and a fourth side. The first side and the third side are aligned in a first plane perpendicular to the conductors and the second side and the fourth side are aligned in a second plane perpendicular to the conductors. The first vias contact the first conductor in only the first side. The second vias contact the third conductor in only the third side. And the second conductor is outside the second plane.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: May 19, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Juhan Kim, Mahbub Rashed, Navneet Jain
  • Patent number: 10658176
    Abstract: One illustrative method disclosed includes, among other things, forming a first dielectric layer and forming first and second conductive structures comprising cobalt embedded in the first dielectric layer. A second dielectric layer is formed above and contacting the first dielectric layer. The first and second dielectric layers comprise different materials, and a portion of the second dielectric layer comprises carbon or nitrogen. A first cap layer is formed above the first and second conductive structures and the second dielectric layer.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: May 19, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Frank W. Mont, Han You, Shariq Siddiqui, Brown C. Peethala
  • Patent number: 10658243
    Abstract: The present disclosure relates to methods for forming replacement metal gate (RMG) structures and related structures. A method may include: forming a portion of sacrificial material around each fin of a set of adjacent fins; forming a first dielectric region between the portions of sacrificial material; forming a second dielectric region on the first dielectric region; forming an upper source/drain region from an upper portion of each fin; removing only the second dielectric region and the sacrificial material; and forming a work function metal (WFM) in place of the second dielectric region and the sacrificial material. The semiconductor structure may include gate structures surrounding adjacent fins; a first dielectric region between the gate structures; a second dielectric region above the first dielectric region and between the gate structures; and a liner between the first dielectric region and the gate structures such that the second dielectric region directly contacts the gate structures.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: May 19, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Daniel Chanemougame, Steven R. Soss, Steven J. Bentley, Chanro Park
  • Patent number: 10649026
    Abstract: A method in which connectivity tests of integrated circuit structures in a die are performed. The connectivity tests are performed at a first level of the die. Potential defect locations are identified in the die indicating via locations susceptible to systematic failure due to via opens or via shorts. The potential defect locations are translated to via locations for a second level of the die. The second level is below the first level. After translating the hot spot, the second level is inspected for defects. The via locations on the first level are inspected for defects. All defects for the second level are translated to the via locations for the first level. A net trace of defects is created using prior level subtraction of the translated defects for the second level and the defects for the first level.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: May 12, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Oliver D. Patterson, Peter Lin, Weihong Gao
  • Patent number: 10651046
    Abstract: Methods of self-aligned multiple patterning. A mandrel is formed over a hardmask, and a planarizing layer is formed over the mandrel and the hardmask. The planarizing layer is patterned to form first and second trenches exposing respective first and second lengthwise sections of the mandrel. A portion of the patterned planarizing layer covers a third lengthwise section of the mandrel arranged between the first and second lengthwise sections of the mandrel. After patterning the planarizing layer, the first and second lengthwise sections of the mandrel are removed with an etching process to define a pattern including a mandrel line exposing respective first portions of the hardmask. The third lengthwise section of the mandrel is masked by the portion of the planarizing layer during the etching process, and the third lengthwise section covers a second portion of the hardmask arranged along the mandrel line between the first portions of the hardmask.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: May 12, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hsueh-Chung Chen, Brendan O'Brien, Martin O'Toole, Keith Donegan
  • Patent number: 10651173
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion cut for gate structures and methods of manufacture. The structure includes: a plurality of fin structures composed of semiconductor material; a plurality of replacement gate structures extending over the plurality of fin structures; a plurality of diffusion regions adjacent to the each of the plurality of replacement gate structures; and a single diffusion break between the diffusion regions of the adjacent replacement gate structures, the single diffusion break being filled with an insulator material. In a first cross-sectional view, the single diffusion break extends into the semiconductor material and in a second cross-sectional view, the single diffusion break is devoid of semiconductor material of the plurality of fin structures.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: May 12, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guowei Xu, Hui Zang, Ruilong Xie, Haiting Wang