Patents Assigned to GLOBALFOUNDRIES Inc.
  • Patent number: 11309220
    Abstract: A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor patterned in a self-aligned process. A plurality of fins is formed. A gate structure is formed on at least a first side and a second side of a lower portion of each fin. A spacer is formed on at least a first side and a second side of an upper portion of each fin. At least one layer is formed above the substrate and between the fins. An opening is formed in the at least one layer between the fins by an etching process. The spacer protects the gate structure during the etching process.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: April 19, 2022
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chanro Park, Ruilong Xie, Min Gyu Sung
  • Patent number: 11300948
    Abstract: A process control method for manufacturing semiconductor devices, including determining a quality metric of a production semiconductor wafer by comparing production scatterometric spectra of a production structure of the production wafer with reference scatterometric spectra of a reference structure of reference semiconductor wafers, the production structure corresponding to the reference structure, the reference spectra linked by machine learning to a reference measurement value of the reference structure, determining a process control parameter value (PCPV) of a wafer processing step, the PCPV determined based on measurement of the production wafer and whose contribution to the PCPV is weighted with a first predefined weight based on the quality metric, and based on a measurement of a different wafer and whose contribution to the PCPV is weighted with a second predefined weight based on the quality metric, and controlling, with the PCPV, the processing step during fabrication.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: April 12, 2022
    Assignees: NOVA LTD, GLOBALFOUNDRIES INC.
    Inventors: Taher Kagalwala, Alok Vaid, Shay Yogev, Matthew Sendelbach, Paul Isbester, Yoav Etzioni
  • Publication number: 20220085994
    Abstract: Methods and systems generate seeds for public-private key pairs by determining a timestamp value associated with a process design kit (PDK) when a user of the PDK triggers a tool of the PDK while designing an integrated circuit device to have a physical unclonable function device (PUF). The methods and systems generate a first value by mapping the timestamp value to data of the user, generate a second value by mapping the timestamp value to configuration data of the PDK, and generate a third value by mapping the timestamp value to layout data of the PDK. A random number is then generated by applying a function to the first value, the second value, and the third value. A public-private encryption key pair is generated using the random number as a first seed number and using a second number generated by the number generation device as a second seed number.
    Type: Application
    Filed: September 15, 2020
    Publication date: March 17, 2022
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Romain H. A. Feuillette, David C. Pritchard, Bernhard J. Wunder, Elizabeth Strehlow
  • Patent number: 11264463
    Abstract: Embodiments of the present invention provide a multiple fin field effect transistor (finFET) with low-resistance gate structure. A metallization line is formed in parallel with the gate, and multiple contacts are formed over the fins which connect the metallization line to the gate. The metallization line provides reduced gate resistance, which allows fewer transistors to be used for providing In-Out (IO) functionality, thereby providing space savings that enable an increase in circuit density.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: March 1, 2022
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guillaume Bouche, Andy Chih-Hung Wei
  • Patent number: 11228325
    Abstract: We disclose multiband receivers for millimeter-wave devices, which may have reduced size and/or reduced power consumption. One multiband receiver comprises a first band path comprising a first passive mixer configured to receive a first input RF signal having a first frequency and to be driven by a first local oscillator signal having a frequency about ? the first frequency; a second band path comprising a second passive mixer configured to receive a second input RF signal having a second frequency and to be driven by a second local oscillator signal having a frequency about ? the second frequency; and a base band path comprising a third passive mixer configured to receive intermediate RF signals during a duty cycle and to be driven by a third local oscillator signal having a frequency about ? the first frequency or about ? the second frequency during the duty cycle.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: January 18, 2022
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Abdellatif Bellaouar, Sher Jiun Fang, Frank Zhang
  • Patent number: 11205033
    Abstract: At least one method, apparatus and system disclosed involves a circuit layout for an integrated circuit device comprising a plurality of wider-than-default metal formations for a functional cell. A design for an integrated circuit device is received. The design comprises at least one functional cell. A first pair of wide metal formations are provided. The first pair of wide metal formations comprise a first metal formation and a second metal placed about a first cell boundary of the functional cell for providing additional space for routing, for high-drive routing, and/or for power routing.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: December 21, 2021
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Lei Yuan, Juhan Kim
  • Patent number: 11201152
    Abstract: A semiconductor device at least one first transistor of a first type disposed above a substrate and comprising a channel wider in one cross-section than tall, wherein the first type is a PFET transistor or an NFET transistor; and at least one second transistor of a second type disposed above the at least one first transistor and comprising a channel taller in the one cross-section than wide, wherein the second type is a PFET transistor or an NFET transistor, and the second type is different from the first type. Methods and systems for forming the semiconductor structure.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: December 14, 2021
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Steven Soss, Steven Bentley, Daniel Chanemougame, Julien Frougier, Bipul Paul, Lars Liebmann
  • Patent number: 11114736
    Abstract: Power combiners having increased output power, such as may be useful in millimeter-wave devices. The power combiner comprise at least two channels, wherein each channel comprises a phase alignment circuit, wherein the phase alignment circuit comprises a first differential input subcircuit comprising a first inverter and a second inverter, and a second differential input subcircuit comprising a third inverter and a fourth inverter, wherein the first inverter, the second inverter, the third inverter, and the fourth inverter each comprise a PMOS transistor and an NMOS transistor each having an adjustable back gate bias voltage. By adjusting the back gate bias voltage, the phases of the signal through each channel may be aligned, which may increase the output power of the power combiner. Methods of increasing output power of such power combiners. Systems for manufacturing devices comprising such power combiners.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: September 7, 2021
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: See Taur Lee, Sher Jiung Fang, Abdellatif Bellaouar
  • Patent number: 11069677
    Abstract: We report a semiconductor device, containing a semiconductor substrate; an isolation feature on the substrate; a plurality of gates on the isolation feature, wherein each gate comprises a gate electrode and a high-k dielectric layer disposed between the gate electrode and the isolation feature and disposed on and in contact with at least one side of the gate electrode; and a fill metal between the plurality of gates on the isolation feature. We also report methods of forming such a device, and a system for manufacturing such a device.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: July 20, 2021
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chanro Park, Ruilong Xie, Kangguo Cheng, Juntao Li
  • Publication number: 20210193204
    Abstract: Disclosed is a reference circuit having an even number m of groups of m parallel-connected magnetic tunnel junctions (MTJs). The MTJs in half of the groups are programmed to have parallel resistances (RP) and the MTJs in the other half are programmed to have anti-parallel resistances (RAP). Switches connect the groups in series, creating a series-parallel resistor network. The total resistance (RT) of the network has low variability and is essentially equal to half the sum of a nominal RP plus a nominal RAP and can be employed as a reference resistance (RREF). Under specific biasing conditions the series-parallel resistor network can generate a low variability reference parameter (XREF) that is dependent on this RREF. Also disclosed are an integrated circuit (IC) that includes the reference circuit and a magnetic random access memory (MRAM) structure, which uses XREF to determine stored data values in MRAM cells and associated methods.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 24, 2021
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Akhilesh Jaiswal, Bipul C. Paul
  • Patent number: 10957544
    Abstract: A method for preserving interlevel dielectric in a gate cut region includes recessing a dielectric fill to expose cap layers of gate structures formed in a device region and in a cut region and forming a liner in the recess on top of the recessed dielectric fill. The liner includes a material to provide etch selectivity to protect the dielectric fill. The gate structures in the cut region are recessed to form a gate recess using the liner to protect the dielectric fill from etching. A gate material is removed from within the gate structure using the liner to protect the dielectric fill from etching. A dielectric gap fill is formed to replace the gate material and to fill the gate recess in the cut region.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: March 23, 2021
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Andrew M. Greene, Ryan O. Jung, Ruilong Xie
  • Patent number: 10957588
    Abstract: Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one self-aligned via within at least dielectric material; plugging the at least one self-aligned via with material; forming a protective sacrificial mask over the material which plugs the at least one self-aligned via, after a recessing process; forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the material during the trench formation; removing the protective sacrificial mask and the material within the at least one self-aligned via to form a wiring via; and filling the wiring via and the at least one trench with conductive material.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: March 23, 2021
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Mark L. Lenhardt, Frank W. Mont, Brown C. Peethala, Shariq Siddiqui, Jessica P. Striss, Douglas M. Trickett
  • Patent number: 10944437
    Abstract: We disclose multiband receivers for millimeter-wave devices, which may have reduced size and/or reduced power consumption. One multiband receiver comprises a first band path comprising a first passive mixer configured to receive a first input RF signal having a first frequency and to be driven by a first local oscillator signal having a frequency about ? the first frequency; a second band path comprising a second passive mixer configured to receive a second input RF signal having a second frequency and to be driven by a second local oscillator signal having a frequency about ? the second frequency; and a base band path comprising a third passive mixer configured to receive intermediate RF signals during a duty cycle and to be driven by a third local oscillator signal having a frequency about ? the first frequency or about ? the second frequency during the duty cycle.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: March 9, 2021
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Abdellatif Bellaouar, Sher Jiun Fang, Frank Zhang
  • Publication number: 20210066503
    Abstract: Test structures for a body-contacted field effect transistor (BCFET) include: a single-pad structure with body contact and probe pad regions connected to a channel region at first and second connection points with a known separation distance between the connection points; and a multi-pad structure with a body contact region connected to a channel region at a first connection point and multiple probe pad regions connected to the channel region at second connection points that are separated from the first connection point by different separation distances.
    Type: Application
    Filed: August 27, 2019
    Publication date: March 4, 2021
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Anupam Dutta, Balaji Swaminathan
  • Publication number: 20210063531
    Abstract: Transmitters having increased efficiency, such as may be useful in millimeter-wave devices. A semiconductor device, comprising a transmitter, comprising a modulator configured to receive a differential input signal having a first frequency and provide a differential modulated signal having the first frequency and a first clock phase; a series comprising one or more frequency multipliers, wherein the series of frequency multipliers is configured to receive the differential modulated signal and provide a differential second signal having a second frequency greater than the first frequency and having a second clock phase; and an output transformer configured to receive the differential second signal and transform the differential second signal to a single-ended output signal. Methods of using such transmitters. Systems for manufacturing devices comprising such transmitters.
    Type: Application
    Filed: August 31, 2019
    Publication date: March 4, 2021
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: See Taur Lee, Sher Jiung Fang
  • Patent number: 10937685
    Abstract: The present disclosure generally relates to semiconductor devices and processing. The present disclosure also relates to isolation structures formed in active regions, more particularly, diffusion break structures in an active semiconductor layer of a semiconductor device. The present disclosure also relates to methods of forming such structures and replacement metal gate processes.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: March 2, 2021
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sipeng Gu, Haiting Wang, Jiehui Shu
  • Patent number: 10937694
    Abstract: Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one non-self-aligned via within at least dielectric material; plugging the at least one non-self-aligned via with material; forming a protective sacrificial mask over the material which plugs the at least one non-self-aligned via, after a recessing process; forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the material during the trench formation; removing the protective sacrificial mask and the material within the at least one non-self-aligned via to form a wiring via; and filling the wiring via and the at least one trench with conductive material.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: March 2, 2021
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Mark L. Lenhardt, Frank W. Mont, Brown C. Peethala, Shariq Siddiqui, Jessica P. Striss, Douglas M. Trickett
  • Patent number: 10937693
    Abstract: At least one method, apparatus and system disclosed herein involves forming local interconnect regions during semiconductor device manufacturing. A plurality of fins are formed on a semiconductor substrate. A gate region is over a portion of the fins. A trench silicide (TS) region is formed adjacent a portion of the gate region. The TS region comprises a first TS metal feature and a second TS metal feature. A bi-layer self-aligned contact (SAC) cap is formed over a first portion of the TS region and electrically coupled to a portion of the gate region. A portion of the bi-layer SAC cap is removed to form a first void. A first local interconnect feature is formed in the first void.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: March 2, 2021
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Andreas Knorr, Haiting Wang, Hui Zang
  • Patent number: 10924058
    Abstract: A CMOS gain element is disclosed herein. Also disclosed herein are splitters, comprising the CMOS gain element, and local oscillator distribution circuitry comprising the splitters and the CMOS gain elements. Semiconductor devices comprising the local oscillator distribution circuitry may have smaller footprints and reduced power consumption relative to prior art devices.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: February 16, 2021
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Abdellatif Bellaouar, Arul Balasubramaniyan
  • Patent number: 10923397
    Abstract: A semiconductor device is provided that includes a substrate, an integrated circuit with a conductive member and a through-substrate-via (TSV) structure. The substrate includes a front surface and a back surface that is opposite the front surface. The integrated circuit with the conductive member is formed over the front surface of the substrate. The TSV structure having vertical sidewalls is formed in the back surface of the substrate connecting with the conductive member. The TSV structure includes a tapered first insulation layer, a conformal conductive layer and a second insulation layer, with the conformal conductive layer positioned between the first and second insulation layers. The conformal conductive layer is electrically connected to the conductive member.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: February 16, 2021
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mohamed A. Rabie, Md Sayed Kaysar Bin Rahim