Patents Assigned to GLOBALFOUNDRIES Inc.
  • Patent number: 10957544
    Abstract: A method for preserving interlevel dielectric in a gate cut region includes recessing a dielectric fill to expose cap layers of gate structures formed in a device region and in a cut region and forming a liner in the recess on top of the recessed dielectric fill. The liner includes a material to provide etch selectivity to protect the dielectric fill. The gate structures in the cut region are recessed to form a gate recess using the liner to protect the dielectric fill from etching. A gate material is removed from within the gate structure using the liner to protect the dielectric fill from etching. A dielectric gap fill is formed to replace the gate material and to fill the gate recess in the cut region.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: March 23, 2021
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Andrew M. Greene, Ryan O. Jung, Ruilong Xie
  • Patent number: 10957588
    Abstract: Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one self-aligned via within at least dielectric material; plugging the at least one self-aligned via with material; forming a protective sacrificial mask over the material which plugs the at least one self-aligned via, after a recessing process; forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the material during the trench formation; removing the protective sacrificial mask and the material within the at least one self-aligned via to form a wiring via; and filling the wiring via and the at least one trench with conductive material.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: March 23, 2021
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Mark L. Lenhardt, Frank W. Mont, Brown C. Peethala, Shariq Siddiqui, Jessica P. Striss, Douglas M. Trickett
  • Patent number: 10944437
    Abstract: We disclose multiband receivers for millimeter-wave devices, which may have reduced size and/or reduced power consumption. One multiband receiver comprises a first band path comprising a first passive mixer configured to receive a first input RF signal having a first frequency and to be driven by a first local oscillator signal having a frequency about ? the first frequency; a second band path comprising a second passive mixer configured to receive a second input RF signal having a second frequency and to be driven by a second local oscillator signal having a frequency about ? the second frequency; and a base band path comprising a third passive mixer configured to receive intermediate RF signals during a duty cycle and to be driven by a third local oscillator signal having a frequency about ? the first frequency or about ? the second frequency during the duty cycle.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: March 9, 2021
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Abdellatif Bellaouar, Sher Jiun Fang, Frank Zhang
  • Publication number: 20210063531
    Abstract: Transmitters having increased efficiency, such as may be useful in millimeter-wave devices. A semiconductor device, comprising a transmitter, comprising a modulator configured to receive a differential input signal having a first frequency and provide a differential modulated signal having the first frequency and a first clock phase; a series comprising one or more frequency multipliers, wherein the series of frequency multipliers is configured to receive the differential modulated signal and provide a differential second signal having a second frequency greater than the first frequency and having a second clock phase; and an output transformer configured to receive the differential second signal and transform the differential second signal to a single-ended output signal. Methods of using such transmitters. Systems for manufacturing devices comprising such transmitters.
    Type: Application
    Filed: August 31, 2019
    Publication date: March 4, 2021
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: See Taur Lee, Sher Jiung Fang
  • Publication number: 20210066503
    Abstract: Test structures for a body-contacted field effect transistor (BCFET) include: a single-pad structure with body contact and probe pad regions connected to a channel region at first and second connection points with a known separation distance between the connection points; and a multi-pad structure with a body contact region connected to a channel region at a first connection point and multiple probe pad regions connected to the channel region at second connection points that are separated from the first connection point by different separation distances.
    Type: Application
    Filed: August 27, 2019
    Publication date: March 4, 2021
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Anupam Dutta, Balaji Swaminathan
  • Patent number: 10937693
    Abstract: At least one method, apparatus and system disclosed herein involves forming local interconnect regions during semiconductor device manufacturing. A plurality of fins are formed on a semiconductor substrate. A gate region is over a portion of the fins. A trench silicide (TS) region is formed adjacent a portion of the gate region. The TS region comprises a first TS metal feature and a second TS metal feature. A bi-layer self-aligned contact (SAC) cap is formed over a first portion of the TS region and electrically coupled to a portion of the gate region. A portion of the bi-layer SAC cap is removed to form a first void. A first local interconnect feature is formed in the first void.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: March 2, 2021
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Andreas Knorr, Haiting Wang, Hui Zang
  • Patent number: 10937694
    Abstract: Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one non-self-aligned via within at least dielectric material; plugging the at least one non-self-aligned via with material; forming a protective sacrificial mask over the material which plugs the at least one non-self-aligned via, after a recessing process; forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the material during the trench formation; removing the protective sacrificial mask and the material within the at least one non-self-aligned via to form a wiring via; and filling the wiring via and the at least one trench with conductive material.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: March 2, 2021
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Mark L. Lenhardt, Frank W. Mont, Brown C. Peethala, Shariq Siddiqui, Jessica P. Striss, Douglas M. Trickett
  • Patent number: 10937685
    Abstract: The present disclosure generally relates to semiconductor devices and processing. The present disclosure also relates to isolation structures formed in active regions, more particularly, diffusion break structures in an active semiconductor layer of a semiconductor device. The present disclosure also relates to methods of forming such structures and replacement metal gate processes.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: March 2, 2021
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sipeng Gu, Haiting Wang, Jiehui Shu
  • Patent number: 10924058
    Abstract: A CMOS gain element is disclosed herein. Also disclosed herein are splitters, comprising the CMOS gain element, and local oscillator distribution circuitry comprising the splitters and the CMOS gain elements. Semiconductor devices comprising the local oscillator distribution circuitry may have smaller footprints and reduced power consumption relative to prior art devices.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: February 16, 2021
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Abdellatif Bellaouar, Arul Balasubramaniyan
  • Patent number: 10923397
    Abstract: A semiconductor device is provided that includes a substrate, an integrated circuit with a conductive member and a through-substrate-via (TSV) structure. The substrate includes a front surface and a back surface that is opposite the front surface. The integrated circuit with the conductive member is formed over the front surface of the substrate. The TSV structure having vertical sidewalls is formed in the back surface of the substrate connecting with the conductive member. The TSV structure includes a tapered first insulation layer, a conformal conductive layer and a second insulation layer, with the conformal conductive layer positioned between the first and second insulation layers. The conformal conductive layer is electrically connected to the conductive member.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: February 16, 2021
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mohamed A. Rabie, Md Sayed Kaysar Bin Rahim
  • Publication number: 20210043727
    Abstract: A gate-all-around field effect transistor (GAAFET) and method. The GAAFET includes nanosheets, a gate around center portions of the nanosheets, and inner spacers aligned below end portions. The nanosheet end portions are tapered from the source/drain regions to the gate and the inner spacers are tapered from the gate to the source/drain regions. Each inner spacer includes: a first spacer layer, which has a uniform thickness and extends laterally from the gate to an adjacent source/drain region; a second spacer layer, which fills the space between a planar top surface of the first spacer layer and a tapered end portion of the nanosheet above; and, for all but the lowermost inner spacers, a third spacer layer, which is the same material as the second spacer layer and which fills the space between a planar bottom surface of the first spacer layer and a tapered end portion of the nanosheet below.
    Type: Application
    Filed: August 7, 2019
    Publication date: February 11, 2021
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Julien Frougier, Ruilong Xie, Kangguo Cheng, Chanro Park
  • Patent number: 10914897
    Abstract: A probe device is configured to insert optical fiber probes directly into a v-groove coupler on an optical integrated circuit (IC) device. The probe device may include a probe holder comprising with a slot. A fiber holder may insert into the slot. The fiber holder may comprise a body with a first portion and second portion disposed at an angle relative to one another so that the first portion is shorter than the second portion. The body may have a bottom with grooves disposed therein, the grooves having dimensions to receive part of an optical fiber probes therein. In use, the fiber holder can arrange the optical fiber probes to extend into the v-grooves of the v-groove coupler of an optical IC on a wafer. The device may incorporate an alignment mechanism that permits the fiber holder to move or “self-align” in response to contact between the optical fiber probes and structure of the v-groove coupler of an optical IC on a wafer.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: February 9, 2021
    Assignee: GlobalFoundries Inc.
    Inventors: Hanyi Ding, John Ferrario, John Joseph Cartier, Benjamin Michael Cadieux
  • Patent number: 10916470
    Abstract: Structures that include a field effect-transistor and methods of forming a structure that includes a field-effect transistor. A first field-effect transistor includes a first source/drain region, and a second field-effect transistor includes a second source/drain region. A first contact is arranged over the first source/drain region, and a second contact is arranged over the second source/drain region. A portion of a dielectric layer, which is composed of a low-k dielectric material, is laterally arranged between the first contact and the second contact.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: February 9, 2021
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Vimal K. Kamineni, Ruilong Xie, Kangguo Cheng, Adra V. Carr
  • Patent number: 10910471
    Abstract: A method of forming a logic or memory cell with an epi-RSD width of larger than 1.3× fin pitch and the resulting device are provided. Embodiments include a device including a RSD region formed on each of a plurality of fins over a substrate, wherein the RSD has a width larger than 1.3× fin pitch, a TS formed on the RSD, and an ILD formed over the TS.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: February 2, 2021
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jianwei Peng, Sang Woo Lim, Matthew Wahlquist Stoker, Huang Liu, Jinping Liu
  • Patent number: 10909443
    Abstract: Embodiments of the present disclosure provide a neuromorphic circuit structure including: a first vertically-extending neural node configured to generate an output signal based on at least one input to the first vertically-extending neural node; an interconnect stack adjacent the vertically-extending neural node, the interconnect stack including a first conducting line coupled to the first vertically-extending neural node and configured to receive the output signal, a second conducting line vertically separated from the first conducting line, and a memory via vertically coupling the first conducting line to the second conducting line; and a second vertically-extending neural node adjacent the interconnect stack, and coupled to the second conducting line for receiving the output signal from the first vertically-extending neural node.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: February 2, 2021
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Edward J. Nowak, Siva P. Adusumilli, Ruilong Xie, Julien Frougier
  • Patent number: 10910276
    Abstract: A structure, an STI structure and a related method are disclosed. The structure may include an active region extending from a substrate; a gate extending over the active region; and a source/drain region in the active region, and an STI structure. The STI structure includes a liner and a fill layer on the liner along the opposed longitudinal sides of a lower portion of the active region, and the fill layer along the opposed ends of the active region. The liner may include a tensile stress-inducing liner that imparts a transverse-to-length tensile stress in at least a lower portion of the active region but not lengthwise. The liner can be applied in an n-FET region and/or a p-FET region to improve performance.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: February 2, 2021
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yongjun Shi, Xinyuan Dou, Chun Yu Wong, Hongliang Shen, Baofu Zhu
  • Patent number: 10910503
    Abstract: The present disclosure generally relates to semiconductor detectors for use in optoelectronic/photonic devices and integrated circuit (IC) chips, and methods for forming same. The present disclosure also relates to photodetectors integrated with waveguide stacks, more particularly, photodetectors with butt-end coupled waveguides. The present disclosure also relates to methods of forming such structures.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: February 2, 2021
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Yusheng Bian, Ajey Poovannummoottil Jacob
  • Publication number: 20210027005
    Abstract: At least one method, apparatus and system disclosed involves a circuit layout for an integrated circuit device comprising a plurality of wider-than-default metal formations for a functional cell. A design for an integrated circuit device is received. The design comprises at least one functional cell. A first pair of wide metal formations are provided. The first pair of wide metal formations comprise a first metal formation and a second metal placed about a first cell boundary of the functional cell for providing additional space for routing, for high-drive routing, and/or for power routing.
    Type: Application
    Filed: October 14, 2020
    Publication date: January 28, 2021
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Lei Yuan, Juhan Kim
  • Patent number: 10903207
    Abstract: Disclosed is an integrated circuit (IC) formation method, wherein trenches are formed within a semiconductor layer to define semiconductor mesa(s). Instead of immediately filling the trenches with an isolation material and performing a planarizing process to complete the STI regions prior to device formation, the method initially only form sidewall spacers within the trenches on the exposed sidewalls of the semiconductor mesa(s). After the sidewall spacers are formed, device(s) (e.g., field effect transistor(s), silicon resistor(s), etc.) are formed using the semiconductor mesa(s) and, optionally, additional device(s) (e.g., polysilicon resistor(s)) can be formed within the trenches between adjacent semiconductor mesas. Subsequently, middle of the line (MOL) dielectrics (e.g., a conformal etch stop layer and a blanket interlayer dielectric (ILD) layer) are deposited over the device(s), thereby filling any remaining space within the trenches and completing the STI regions.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: January 26, 2021
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Anthony K. Stamper, Steven M. Shank, Siva P. Adusumilli
  • Patent number: 10903118
    Abstract: Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one non-self-aligned via within at least dielectric material; plugging the at least one non-self-aligned via with material; forming a protective sacrificial mask over the material which plugs the at least one non-self-aligned via, after a recessing process; forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the material during the trench formation; removing the protective sacrificial mask and the material within the at least one non-self-aligned via to form a wiring via; and filling the wiring via and the at least one trench with conductive material.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: January 26, 2021
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Mark L. Lenhardt, Frank W. Mont, Brown C. Peethala, Shariq Siddiqui, Jessica P. Striss, Douglas M. Trickett