Abstract: A memory structure includes a first memory array with two transistor-two variable resistor memory cells and a second memory array with one transistor-one variable resistor memory cells, which are each selectively operable in read, write and standby modes. The first memory array and the second memory array are interleaved so that, when the second memory operates in the read mode, the first memory array automatically and concurrently operates in a reference mode. A method of operating the memory structure includes, when the second memory array operates in the read mode, automatically and concurrently operating the first memory array in the reference mode so that the first memory array generates and outputs a statistical reference voltage, which is between the low and high voltages of a nominal memory cell within the second memory array and which is employed by the second memory array to sense a stored data value.

Abstract: Two pairs of alignment targets (one aligned, one misaligned by a bias distance) are formed on different masks to produce a first pair of conjugated interference patterns. Other pairs of alignment targets are also formed on the masks to produce a second pair of conjugated interference patterns that are inverted the first. Misalignment of the dark and light regions of the first interference patterns and the second interference patterns in both pairs of conjugated interference patterns is determined when patterns formed using the masks are overlaid. A magnification factor (of the interference pattern misalignment to the target misalignment) is calculated as a ratio of the difference of misalignment of the relatively dark and relatively light regions in the pairs of interference patterns, over twice the bias distance. The interference pattern misalignment is divided by the magnification factor to produce a self-referenced and self-calibrated target misalignment amount, which is then output.

Abstract: Structures for a memory cell and methods associated with forming and using such structures. The structure includes a silicon-on-insulator wafer including a device layer, a substrate, and a buried insulator layer between the device layer and the substrate. The structure further includes a field-effect transistor having first and second source/drain regions and a gate electrode that are over the buried insulator layer. A moat region is arranged in the substrate beneath the field-effect transistor, a well is arranged in the substrate beneath the moat region, and an isolation region extends through the device layer and the buried insulator layer into the substrate. The isolation region is arranged to surround a portion of the device layer defining an active region for the field-effect transistor and a portion of the moat region. A fence region, which extends between the well and the isolation region, surrounds the portion of the moat region.

Abstract: A memory structure includes a first memory array with two transistor-two variable resistor memory cells and a second memory array with one transistor-one variable resistor memory cells, which are each selectively operable in read, write and standby modes. The first memory array and the second memory array are interleaved so that, when the second memory operates in the read mode, the first memory array automatically and concurrently operates in a reference mode. A method of operating the memory structure includes, when the second memory array operates in the read mode, automatically and concurrently operating the first memory array in the reference mode so that the first memory array generates and outputs a statistical reference voltage, which is between the low and high voltages of a nominal memory cell within the second memory array and which is employed by the second memory array to sense a stored data value.

Abstract: One device disclosed herein includes a gate above a semiconductor substrate, the gate comprising a gate structure and a gate cap, and conductive source/drain metallization structures adjacent the gate, each of the conductive source/drain metallization structures having a front face and a recess defined in each of the conductive source/drain metallization structures. In this example, the device further includes a spacer structure comprising recess filling portions that substantially fill the recesses and a portion that extends across a portion of the upper surface of the gate cap, wherein a portion of the gate cap is exposed within the spacer structure, an insulating material within the spacer structure and on the exposed portion of the gate cap, a gate contact opening that exposes a portion of an upper surface of the gate structure, and a conductive gate contact structure in the conductive gate contact opening.

Abstract: A method of forming a gate structure with an undercut region includes, among other things, forming a plurality of fins above a substrate and an isolation structure above the substrate and between the plurality of fins, forming a placeholder gate structure above the plurality of fins in a first region and above the isolation structure in a second region, selectively removing a portion of the placeholder structure in the second region to define an undercut recess, forming a spacer structure adjacent the sacrificial gate structure, forming a dielectric layer adjacent the spacer structure and in the undercut recess, removing remaining portions of the placeholder gate structure to define a gate cavity, and forming a replacement gate structure in the gate cavity.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to rounded shaped transistors and methods of manufacture. The structure includes a gate structure composed of a metal electrode and a rounded ferroelectric material which overlaps an active area in a width direction into an isolation region.

Abstract: Methods of forming cross-coupling contacts for field-effect transistors and structures for field effect-transistors that include cross-coupling contacts. A dielectric cap is formed over a gate structure and a sidewall spacer adjacent to a sidewall of the gate structure. A portion of the dielectric cap is removed from over the sidewall spacer and the gate structure to expose a first portion of the gate electrode of the gate structure at a top surface of the gate structure. The sidewall spacer is then recessed relative to the gate structure to expose a portion of the gate dielectric layer at the sidewall of the gate structure, which is removed to expose a second portion of the gate electrode of the gate structure. A cross-coupling contact is formed that connects the first and second portions of the gate electrode of the gate structure with an epitaxial semiconductor layer adjacent to the sidewall spacer.

Abstract: Structures that include stacked field-effect transistors and methods for forming a structure that includes stacked field-effect transistors. A structure includes a first fin, a second fin arranged over the first fin, a first dielectric layer between the first fin and the second fin, and a first inverter. The first inverter includes a first field-effect transistor with a channel region in the first fin and a second field-effect transistor with a channel region in the second fin. The first field-effect transistor and the second field-effect transistor share a first gate structure having an overlapping arrangement with the channel region in the first fin and the channel region in the second fin. The first fin has a longitudinal axis, and the second fin has a longitudinal axis that is aligned at an angle relative to the longitudinal axis of the first fin.

Abstract: The present disclosure relates to an isolation region between semiconductor devices and methods of fabrication. Embodiments include device having a silicon-on-insulator (SOI) substrate; a dummy gate between two metal gates formed over the SOI substrate, the dummy gate providing a physical diffusion break between the two metal gates; raised source/drain (S/D) regions formed on sides of the metal gates; and interlayer dielectric formed over the dummy gate, raised S/D regions and metal gates and in openings on sides of the dummy gate.

Abstract: A method of fabricating interconnects in a semiconductor device is provided, which includes forming a metallization layer and depositing a hardmask layer over the metallization layer. A dielectric layer is deposited over the hardmask layer and an opening is formed in the dielectric layer to expose the hardmask layer. The exposed hardmask layer in the opening is etched to form an undercut beneath the dielectric layer. A metal shoulder is formed at the undercut, wherein the metal shoulder defines an aperture dimension used for forming a via opening extending to the metallization layer.

Abstract: Fabrication methods and device structures for a silicon controlled rectifier. A cathode is arranged over a top surface of a substrate and a well is arranged beneath the top surface of the substrate. The cathode is composed of a semiconductor material having a first conductivity type, and the well also has the first conductivity type. A semiconductor layer, which has a second conductivity type opposite to the first conductivity type, includes a section over the top surface of the substrate. The section of the semiconductor layer is arranged to form an anode that adjoins the well along a junction.

Abstract: Methods of forming a structure that includes a field-effect transistor and structures that include a field effect-transistor. A cut is formed that extends through a gate structure of the field-effect transistor such that a gate electrode of the gate structure is divided into a first section having a first surface and a second section having a second surface spaced across the cut from the first surface. After forming the cut, a first section of a conductive layer is selectively deposited on the first surface of the first section of the gate electrode and a second section of the conductive layer is selectively deposited on the second surface of the second section of the gate electrode to shorten the cut. A dielectric material is deposited in the cut between the first and second sections of the conductive layer on the first and second surfaces of the gate electrode to form a dielectric pillar.

Abstract: Structures for a waveguide bend and methods of fabricating a structure for a waveguide bend. A first waveguide core has a first section, a second section, and a first waveguide bend connecting the first section with the second section. The first waveguide core has a first side surface extending about an outer radius of the first waveguide bend. A second waveguide core also has a first section, a second section, and a second waveguide bend connecting the first section with the second section. The second waveguide core has a second side surface extending about an outer radius of the second waveguide bend. The first waveguide bend is spaced from the second waveguide bend in a first non-contacting relationship with a gap between the first side surface and the second side surface. The gap has a perpendicular distance selected to permit optical signal transfer between the first and second waveguide bends.

Abstract: The present disclosure relates to circuit structures and, more particularly, to circuit structures which detect high speed and high precision characterization of VTsat and VTlin of FET arrays and methods of manufacture and use. The circuit includes a control loop comprised of a differential amplifier, a plurality of FET arrays, and at least one analog switch enabling selection between a calibration mode and an operation mode.

Abstract: Disclosed are a process design kit (PDK) for integrated circuit (IC) designs and a computer-aided design (CAD) system that employs the PDK. The PDK includes a design scan script. When the script is executed by the CAD system, previously generated and stored IC designs are scanned and a report with cell use information (CUI) is generated. The CUI indicates the different parameterized cells (pcells) and different configurations thereof contained in the IC designs. Also disclosed is a PDK development system, which receives CUI reports from CAD system(s), compiles the CUI, and revises the PDK (i.e., develops an update or upgrade) based, in part, on the complied CUI. For example, the complied CUI can indicate critical targets that require a regression analysis during the PDK revision process. By limiting regression analyses to identified critical targets, the turn around time and costs associated with revising the PDK are significantly reduced.

Abstract: Structures that integrate airgaps with a field-effect transistor and methods for forming a field-effect transistor with integrated airgaps. A first semiconductor layer is formed on a substrate, and a second semiconductor layer is formed over the first semiconductor layer. A source/drain region of a field-effect transistor is formed in the second semiconductor layer. An airgap is located in the first semiconductor layer, The airgap is arranged in a vertical direction between the source/drain region and the substrate.

Abstract: A method of forming a buried local interconnect is disclosed including, among other things, forming a first sacrificial layer embedded between a first semiconductor layer and a second semiconductor layer, forming a plurality of fin structures above the second semiconductor layer, forming a mask layer having an opening positioned between an adjacent pair of the fin structures, removing a portion of the second semiconductor layer exposed by the opening to expose the first sacrificial layer and define a first cavity in the second semiconductor layer, removing portions of the first sacrificial layer positioned between the first semiconductor layer and the second semiconductor layer to form lateral cavity extensions of the first cavity, forming a first liner layer in the first cavity, and forming a conductive interconnect in the first cavity over the first liner layer.

Abstract: We disclose multiband receivers for millimeter-wave devices, which may have reduced size and/or reduced power consumption. One multiband receiver comprises a first band path comprising a first passive mixer configured to receive a first input RF signal having a first frequency and to be driven by a first local oscillator signal having a frequency about ? the first frequency; a second band path comprising a second passive mixer configured to receive a second input RF signal having a second frequency and to be driven by a second local oscillator signal having a frequency about ? the second frequency; and a base band path comprising a third passive mixer configured to receive intermediate RF signals during a duty cycle and to be driven by a third local oscillator signal having a frequency about ? the first frequency or about ? the second frequency during the duty cycle.

Abstract: A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.