Patents Assigned to GLOBALFOUNDRIES Inc.
  • Patent number: 10797049
    Abstract: A FinFET structure having reduced effective capacitance and including a substrate having at least two fins thereon laterally spaced from one another, a metal gate over fin tops of the fins and between sidewalls of upper portions of the fins, source/drain regions in each fin on opposing sides of the metal gate, and a dielectric bar within the metal gate located between the sidewalls of the upper portions of the fins, the dielectric bar being laterally spaced away from the sidewalls of the upper portions of the fins within the metal gate.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: October 6, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Haiting Wang, Chung Foong Tan, Guowei Xu, Ruilong Xie, Scott H. Beasor, Liu Jiang
  • Patent number: 10796056
    Abstract: Original cell design rule violations with respect to a second wiring layer are identified, while conductors of the second wiring layer are in an original position. The conductors of the second wiring layer are offset into different offset positions, and then the process of identifying violations is repeated for each of the offset positions. With this, metrics are generated for the original cell for the original position and each of the offset positions. Then, the original cell or the pitch of the second wiring layer are altered to produce alterations. The processes of identifying violations, offsetting conductors in the second wiring layer, repeating the identification of violations for all offsets, and generating metrics are repeated for each of the alterations. The original cell or one of the alterations is then selected, based on which cell produces the lowest number of violations of the design rules.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: October 6, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Gregory A. Northrop, Lionel Riviere-Cazaux, Lars Liebmann, Kai Sun, Norihito Nakamoto
  • Patent number: 10796973
    Abstract: Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a device-under-testing that has one or more source/drain regions and a first metallization level arranged over the device-under-testing. The first metallization level includes one or more first interconnect lines. The structure further includes a contact level having one or more first contacts arranged between the first metallization level and the device-under-testing. The one or more first contacts directly connect the one or more first interconnect lines with the one or more source/drain regions. The structure further includes a second metallization level arranged over the first metallization level. The second metallization level has a first test pad and one or more second interconnect lines connecting the one or more first interconnect lines with the first test pad.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: October 6, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Mankyu Yang, Vara Govindeswara Reddy Vakada, Edward Maciejewski, Brian Greene, Atsushi Ogino, Vikrant Chauhan, Prianka Sengupta
  • Patent number: 10797138
    Abstract: Methods of forming contacts for vertical-transport field-effect transistors and structures for a vertical-transport field-effect transistor and contact. An interlayer dielectric layer is deposited over a gate stack, and a first opening is formed in the interlayer dielectric layer and penetrates through the gate stack to cut the gate stack into a first section and a second section. A dielectric pillar is formed in the first opening and is arranged between the first section of the gate stack and the second section of the gate stack. Second and third openings are formed in the interlayer dielectric layer that penetrate to the gate stack and that are divided by the dielectric pillar. A first contact in the second opening is coupled with the first section of the gate stack, and a second contact in the third opening is coupled with the second section of the gate stack.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: October 6, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Emilie Bourjot, Daniel Chanemougame, Steven Bentley
  • Publication number: 20200313269
    Abstract: Power combiners having increased output power, such as may be useful in millimeter-wave devices. The power combiner comprise at least two channels, wherein each channel comprises a phase alignment circuit, wherein the phase alignment circuit comprises a first differential input subcircuit comprising a first inverter and a second inverter, and a second differential input subcircuit comprising a third inverter and a fourth inverter, wherein the first inverter, the second inverter, the third inverter, and the fourth inverter each comprise a PMOS transistor and an NMOS transistor each having an adjustable back gate bias voltage. By adjusting the back gate bias voltage, the phases of the signal through each channel may be aligned, which may increase the output power of the power combiner. Methods of increasing output power of such power combiners. Systems for manufacturing devices comprising such power combiners.
    Type: Application
    Filed: March 31, 2020
    Publication date: October 1, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: See Taur Lee, Sher Jiung Fang, Abdellatif Bellaouar
  • Patent number: 10790276
    Abstract: Methods, apparatus, and systems relating to a MOSFET with ESD resistance, specifically, to a semiconductor device comprising a field-effect transistor (FET) comprising a gate, a source, and a drain, all extending parallel to each other in a first direction; at least one source electrostatic discharge (ESD) protection circuit; a source terminal disposed above and in electrical contact with the at least one source ESD protection circuit, wherein the source terminal extends in the first direction; at least one drain ESD protection circuit; and a drain terminal disposed above and in electrical contact with the at least one drain ESD protection circuit, wherein the drain terminal extends in the first direction.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: September 29, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chien-Hsin Lee, Manjunatha Prabhu, Mahadeva Iyer Natarajan
  • Patent number: 10790204
    Abstract: Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a test pad, a device-under-testing having one or more source/drain regions, and a metallization level arranged over the device-under-testing. The metallization level includes one or more interconnect lines that are connected with the test pad. One or more contacts, which are arranged between the metallization level and the device-under-testing, directly connect the one or more interconnect lines with the one or more source/drain regions.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: September 29, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Mankyu Yang, Vara Govindeswara Reddy Vakada, Edward Maciejewski, Brian Greene, Atsushi Ogino, Vikrant Chauhan, Prianka Sengupta
  • Patent number: 10790198
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to fin structures and methods of manufacture. The structure includes: a plurality of fin structures formed of substrate material; a semiconductor material located between selected fin structures of the plurality of fin structures; and isolation regions within spaces between the plurality of fin structures.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: September 29, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Fuad H. Al-Amoody, Yiheng Xu, Rishikesh Krishnan
  • Patent number: 10788877
    Abstract: Embodiments of the disclosure provide a low power multiplexer (MUX) circuit, including: a first data input coupled to an input of a first pass gate device; a second data input coupled to an input of a second pass gate device; a hold latch having an input coupled to a data output of the MUX circuit and an output coupled to an input of a supplemental pass gate device; and a pulse generator for generating a HOLD pulse signal, wherein the HOLD pulse signal is coupled to a control input of the supplemental pass gate device. The hold latch is configured to hold a previously valid output data signal of the MUX circuit until a valid input data signal is available at the first data input or the second data input.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: September 29, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sebastian T. Ventrone, Lansing D. Pickup
  • Patent number: 10788806
    Abstract: A method for initializing individual exposure field parameters of an overlay controller is disclosed including initializing a first control thread having a first context associated with a first product type, wherein a first layout of first exposure fields is defined for the first product type for processing in a stepper. The method further includes remapping a set of previous control state data for a set of control threads associated with other product types different than the first product type into the first layout. The other product types have layouts of second exposure fields different than the first layout. An initial set of control state data for the first control thread associated with the first product type is generated using the remapped previous control state data. The stepper is configured for processing a first substrate of the first product type using the initial set of control state data.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: September 29, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Richard P. Good, Eyup Cinar
  • Patent number: 10790785
    Abstract: Embodiments of the present disclosure provide a circuit structure. An error amplifier of the structure includes an input terminal coupled to a voltage source, a reference terminal, and an output terminal coupled to a back-gate terminal of a power amplifier. A voltage at the output terminal of the error amplifier indicates a voltage difference between the input terminal and the reference terminal. A logarithmic current source may be coupled to the reference terminal of the error amplifier, the logarithmic current being configured to generate a reference current logarithmically proportionate to a voltage level of the voltage source. A plurality of serially coupled transistor cells, having a shared substrate and coupled between the reference terminal of the error amplifier and ground, each may include a back-gate terminal coupled to the output terminal of the error amplifier.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: September 29, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yiching Chen, Thomas G. Mckay
  • Patent number: 10790789
    Abstract: In an exemplary structure, a transformer has a primary side and a secondary side. Output from the primary side is coupled to the secondary side. A first power supply is connected to a center tap of the primary side of the transformer. An oscillator includes a first transistor and a second transistor. The front-gate of the first transistor is connected to the drain of the second transistor and the primary side of the transformer. The front-gate of the second transistor is connected to the drain of the first transistor and the primary side of the transformer. A third transistor is connected to the first transistor and a fourth transistor is connected to the second transistor. The third and fourth transistors inject a desired frequency to the oscillator. A voltage source is connected to the back-gate of the first transistor and the back-gate of the second transistor.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: September 29, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: See T. Lee, Abdellatif Bellaouar
  • Patent number: 10790376
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to contact structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions and sidewall spacers; contacts connecting to at least one gate structure of the plurality of gate structures; and at least one metallization feature connecting to the source and drain regions and extending over the sidewall spacers.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: September 29, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Chanro Park, Julien Frougier, Kangguo Cheng, Andre P. Labonte
  • Patent number: 10790148
    Abstract: A method of manufacturing a semiconductor device includes forming a composite spacer architecture over sidewalls of a sacrificial gate disposed over a semiconductor layer, and the subsequent deposition of a supplemental sacrificial gate over the sacrificial gate. A recess etch of the composite spacer architecture is followed by the formation within the recess of a sacrificial capping layer. The supplemental sacrificial gate and the sacrificial gate are removed to expose the composite spacer architecture, which is selectively etched to form a T-shaped cavity overlying a channel region of the semiconductor layer. A replacement metal gate is formed within a lower region of the T-shaped cavity, and a self-aligned contact (SAC) capping layer is formed within an upper region of the T-shaped cavity prior to metallization of the device.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: September 29, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Heimanu Niebojewski, Ruilong Xie, Andrew M. Greene
  • Patent number: 10790363
    Abstract: The disclosure relates to methods of forming integrated circuit (IC) structures with a metal cap on a cobalt layer for source and drain regions of a transistor. An integrated circuit (IC) structure according to the disclosure may include: a semiconductor fin on a substrate; a gate structure over the substrate, the gate structure having a first portion extending transversely across the semiconductor fin; an insulator cap positioned on the gate structure above the semiconductor fin; a cobalt (Co) layer on the semiconductor fin adjacent to the gate structure, wherein an upper surface of the Co layer is below an upper surface of the gate structure; and a metal cap on the Co layer.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: September 29, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Laertis Economikos, Kevin J. Ryan, Ruilong Xie, Hui Zang
  • Patent number: 10784119
    Abstract: Methods of self-aligned multiple patterning. First and second mandrels are formed over a hardmask, and a conformal spacer layer is deposited over the first mandrel, the second mandrel, and the hardmask between the first mandrel and the second mandrel. A planarizing layer is patterned to form first and second trenches that expose first and second lengthwise portions of the conformal spacer layer respectively between the first and second mandrels. After patterning the planarizing layer, the first and second lengthwise portions of the conformal spacer layer are removed with an etching process to expose respective portions of the hardmask along a non-mandrel line. A third lengthwise portion of the conformal spacer layer is masked during the etching process by a portion of the planarizing layer and defines a non-mandrel etch mask.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: September 22, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ravi Prakash Srivastava, Hsueh-Chung Chen, Steven McDermott, Martin O'Toole, Brendan O'Brien, Terry A. Spooner
  • Patent number: 10784846
    Abstract: Embodiments of the disclosure provide a differential clock duty cycle correction (DCC) circuit, including: a hybrid current injector including current sources for generating a correction current, wherein the correction current is added to a clock signal of a first polarity at a first correction node and subtracted from a clock signal of an opposite polarity at a second correction node, and wherein a plurality of the current sources in the hybrid current injector are controlled by a first portion of a n-bit DAC code to generate the correction current; and a current DAC for receiving a second, different portion of the n-bit DAC code and for outputting a corresponding reference current to the current sources in the hybrid current injector, wherein the current sources generate the correction current in response to the reference current output by the current DAC for the second portion of the n-bit DAC code.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: September 22, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: William L. Bucossi, Barry L. Stakely
  • Patent number: 10784342
    Abstract: Structures that include a single diffusion break and methods of forming a single diffusion break. A source/drain region is arranged inside a first cavity in a semiconductor fin, and a dielectric layer is arranged inside a second cavity in the semiconductor fin. A liner, which is composed of a dielectric material, includes a section that is arranged inside the second cavity laterally between the dielectric layer and the source/drain region.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: September 22, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wei Hong, Hong Yu, Jianwei Peng, Hui Zhan
  • Patent number: 10784171
    Abstract: A device is disclosed that includes a first transistor device of a first type and a second transistor device of a second type positioned vertically above the first transistor, wherein the first type and second type of transistors are opposite types. The device also includes a gate structure for the first transistor and the second transistor, wherein the gate structure comprises a first gate electrode for the first transistor and a second gate electrode for the second transistor and a gate stack spacer positioned vertically between the first gate electrode and the second gate electrode so as to electrically isolate the first gate electrode from the second gate electrode.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: September 22, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Julien Frougier, Ruilong Xie, Puneet Harischandra Suvarna
  • Patent number: 10784143
    Abstract: Structures that include a field effect-transistor and methods of forming a structure that includes a field-effect transistor. A semiconductor fin has an upper portion and a lower portion, and a trench isolation region surrounds the lower portion of the semiconductor fin. The trench isolation region has a top surface arranged above the lower portion of the semiconductor fin and arranged below the upper portion of the semiconductor fin. A dielectric layer arranged over the top surface of the trench isolation region. The dielectric layer is composed of a low-k dielectric material.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: September 22, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haiting Wang, Guowei Xu, Hui Zang, Yue Zhong