Patents Assigned to GLOBALFOUNDRIES Inc.
  • Differential clock duty cycle correction with hybrid current injectors and tapered digital to analog converter
    Patent number: 10784846
    Abstract: Embodiments of the disclosure provide a differential clock duty cycle correction (DCC) circuit, including: a hybrid current injector including current sources for generating a correction current, wherein the correction current is added to a clock signal of a first polarity at a first correction node and subtracted from a clock signal of an opposite polarity at a second correction node, and wherein a plurality of the current sources in the hybrid current injector are controlled by a first portion of a n-bit DAC code to generate the correction current; and a current DAC for receiving a second, different portion of the n-bit DAC code and for outputting a corresponding reference current to the current sources in the hybrid current injector, wherein the current sources generate the correction current in response to the reference current output by the current DAC for the second portion of the n-bit DAC code.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: September 22, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: William L. Bucossi, Barry L. Stakely
  • Trench isolation preservation during transistor fabrication
    Patent number: 10784143
    Abstract: Structures that include a field effect-transistor and methods of forming a structure that includes a field-effect transistor. A semiconductor fin has an upper portion and a lower portion, and a trench isolation region surrounds the lower portion of the semiconductor fin. The trench isolation region has a top surface arranged above the lower portion of the semiconductor fin and arranged below the upper portion of the semiconductor fin. A dielectric layer arranged over the top surface of the trench isolation region. The dielectric layer is composed of a low-k dielectric material.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: September 22, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haiting Wang, Guowei Xu, Hui Zang, Yue Zhong
  • Single diffusion breaks formed with liner protection for source and drain regions
    Patent number: 10784342
    Abstract: Structures that include a single diffusion break and methods of forming a single diffusion break. A source/drain region is arranged inside a first cavity in a semiconductor fin, and a dielectric layer is arranged inside a second cavity in the semiconductor fin. A liner, which is composed of a dielectric material, includes a section that is arranged inside the second cavity laterally between the dielectric layer and the source/drain region.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: September 22, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wei Hong, Hong Yu, Jianwei Peng, Hui Zhan
  • Formation of enhanced faceted raised source/drain epi material for transistor devices
    Patent number: 10777642
    Abstract: One illustrative method disclosed herein may include forming a first straight sidewall spacer adjacent a gate structure of a transistor, forming a second straight sidewall spacer on the first straight sidewall spacer and forming a recessed layer of sacrificial material adjacent the second straight sidewall spacer such that the recessed layer of sacrificial material covers an outer surface of a first vertical portion of the second straight sidewall spacer while exposing a second vertical portion of the second straight sidewall spacer. In this example, the method may also include removing the second vertical portion of the second straight sidewall spacer, removing the recessed layer of sacrificial material and forming an epi material such that an edge of the epi material engages the outer surface of the first vertical portion of the second straight sidewall spacer.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: September 15, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Wei Hong, George R. Mulfinger, Hui Zang, Liu Jiang, Zhenyu Hu
  • Bipolar junction transistors with a self-aligned emitter and base
    Patent number: 10777668
    Abstract: Device structures and fabrication methods for a bipolar junction transistor. A trench isolation region surrounds an active region that includes a collector. A base layer is arranged over the active region, and a semiconductor layer is arranged on the base layer. The semiconductor layer includes a stepped profile with a first section having a first width adjacent to the base layer and a second section having a second width that is less than the first width. An emitter is arranged on the second section of the semiconductor layer.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: September 15, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Vibhor Jain, John J. Pekarik, Qizhi Liu, Pernell Dongmo
  • Integrated circuit product with a multi-layer single diffusion break and methods of making such products
    Patent number: 10777637
    Abstract: One illustrative integrated circuit product disclosed herein includes a single diffusion break (SDB) isolation structure positioned between a first fin portion and a second fin portion, wherein the first fin portion comprises a first end surface and the second fin portion comprises a second end surface. In this example, the SDB structure includes a conformal liner layer that engages the first end surface of the first fin portion and the second end surface of the second fin portion, an insulating material positioned on the conformal liner layer, a cap structure positioned above an upper surface of the insulating material and an air gap positioned between a bottom surface of the cap structure and the upper surface of the insulating material.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: September 15, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hong Yu, Jiehui Shu, Hui Zang
  • Integration of vertical-transport transistors and planar transistors
    Patent number: 10777465
    Abstract: Structures including a vertical-transport field-effect transistor and a planar field-effect transistor, and methods of forming such structures. First and second sacrificial fins are respectively formed over first and second areas of the first device region. One or more semiconductor fins of the vertical-transport field-effect transistor are formed over the second device region. A first gate electrode of the planar field-effect transistor, which is arranged on the first device region between the first sacrificial fin and the second sacrificial fin, and a second gate electrode of the vertical-transport field-effect transistor, which is wrapped about the one or more semiconductor fins, are currently formed.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: September 15, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Chun-chen Yeh, Kangguo Cheng, Tenko Yamashita
  • Formation of epi source/drain material on transistor devices and the resulting structures
    Patent number: 10777463
    Abstract: One illustrative device disclosed herein includes an epi cavity formed in a semiconductor substrate adjacent a gate structure of a transistor and an epi semiconductor material comprising first and second portions. The first portion of the epi semiconductor material is positioned within the epi cavity. The second portion of the epi semiconductor material is positioned above the first portion of the epi semiconductor material and above a level corresponding to a level of an upper surface of the semiconductor substrate. The first portion of the epi semiconductor material has a first dimension in a direction corresponding to a gate length direction of the transistor and the second portion of the epi semiconductor material has a second dimension in a direction corresponding to the gate length direction of the transistor, wherein the first dimension is greater than the second dimension.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: September 15, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Man Gu, Tao Han
  • CMOS-based integrated circuit products with isolated P-wells for body-biasing transistor devices
    Patent number: 10777558
    Abstract: One illustrative integrated circuit product disclosed herein comprises a PFET region and an NFET region defined in an active semiconductor layer of an SOI substrate, a deep N-well region positioned in the base semiconductor substrate, first and second isolated P-wells positioned in the base semiconductor substrate below the PFET region and the NFET region, respectively, wherein the first and second isolated P-wells engage the deep N-well region, and a deep isolation structure that extends into the deep N-well region, wherein a first portion of the deep isolation structure is laterally positioned between the first isolated P-well and the second isolated P-well to electrically isolate, in a horizontal direction, the first isolated P-well from the second isolated P-well. The product also includes at least one PFET transistor and at least one NFET transistor.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: September 15, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Juhan Kim
  • Interconnects with non-mandrel cuts formed by early block patterning
    Patent number: 10777413
    Abstract: Methods of fabricating an interconnect structure. A hardmask is deposited over a dielectric layer, and a block mask is formed that is arranged over an area on the hardmask. After forming the block mask, a first mandrel and a second mandrel are formed on the hardmask. The first mandrel is laterally spaced from the second mandrel, and the area on the hardmask is arranged between the first mandrel and the second mandrel. The block mask may be used to provide a non-mandrel cut separating the tips of interconnects subsequently formed in the dielectric layer.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: September 15, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yuping Ren, Guoxiang Ning, Haigou Huang, Sunil K. Singh
  • Bitcells for a non-volatile memory device
    Patent number: 10777607
    Abstract: Structures for a bitcell of a non-volatile memory and methods of fabricating such structures. A field-effect transistor of the bitcell includes a gate having gate electrodes that are arranged in a four contacted (poly) pitch layout. An interconnect structure is arranged over the field-effect transistor, and a memory element arranged in the interconnect structure. The memory element is connected by the interconnect structure with the field-effect transistor.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: September 15, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Bipul C. Paul, Anuj Gupta
  • Back-gate biasing voltage divider topology circuit structure
    Patent number: 10775826
    Abstract: Embodiments of the present disclosure provide a circuit structure including: a first tap node, a first operational element coupled to the first tap node, the first operational element including at least one transistor having a back-gate, a second tap node coupled to the first operational unit, a second operational element coupled to the second tap node, the second operational element including at least one transistor having a back-gate, and a first back-gate biasing voltage regulator coupled to the second operational element and the first tap node. The first back-gate biasing voltage regulator is configured to supply the at least one transistor of the second operational element with a back-gate biasing voltage level that is different than a voltage level available to the second operational element from the second tap node.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: September 15, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ulrich G. Hensel, Jurgen Faul, Arif A. Siddiqi
  • ROV hot-stab with integrated sensor
    Patent number: 10774620
    Abstract: An ROV hot-stab device (100) comprising a hot stab body (102) having a flow bore (102A) that is adapted to receive a fluid, a housing (104) that is operatively coupled to the hot stab body (102), and at least one fluid inlet/outlet (104A/104B) defined in the housing (104). The device (100) also includes an isolation valve (103) that is at least partially positioned within the housing (104) wherein the isolation valve (103) is adapted to, when actuated, establish fluid communication between the bore (102A) of the hot stab body (102) and the at least one fluid inlet/outlet (104A/104B) and at least one sensor (114) positioned at least partially within the housing (104) wherein the sensor (114) is adapted to sense a parameter of the fluid.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: September 15, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Mark Alan Johnson
  • MULTIPLE FIN FINFET WITH LOW-RESISTANCE GATE STRUCTURE
    Publication number: 20200286998
    Abstract: Embodiments of the present invention provide a multiple fin field effect transistor (finFET) with low-resistance gate structure. A metallization line is formed in parallel with the gate, and multiple contacts are formed over the fins which connect the metallization line to the gate. The metallization line provides reduced gate resistance, which allows fewer transistors to be used for providing In-Out (IO) functionality, thereby providing space savings that enable an increase in circuit density.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 10, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Guillaume Bouche, Andy Chih-Hung Wei
  • Through-silicon vias for heterogeneous integration of semiconductor device structures
    Patent number: 10770374
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to through-silicon vias (TSV) for heterogeneous integration of semiconductor device structures and methods of manufacture. The structure includes: a plurality of cavity structures provided in a single substrate; at least one optical device provided on two sides of the single substrate and between the plurality of cavity structures; and a through wafer optical via extending through the substrate, between the plurality of cavity structures and which exposes a backside of the at least one optical device.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: September 8, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Siva P. Adusumilli, Steven M. Shank
  • System comprising a single wafer, reduced volume process chamber
    Patent number: 10770338
    Abstract: One illustrative system disclosed herein includes a process chamber positioned within a processing tool and a wafer chuck that is adapted to be positioned at a wafer processing position located within the process chamber and at a chuck wafer transfer position located outside of the process chamber.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: September 8, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Wieland Pethe, Dirk Noack
  • Self-aligned buried contact for vertical field-effect transistor and method of production thereof
    Patent number: 10770585
    Abstract: A device including a self-aligned buried contact between spacer liners and isolated from a pull down (PD)/pull-up (PU) shared gate and an n-channel field-effect transistor (NFET) pass gate (PG) gate and method of production thereof. Embodiments include first and second high-k/metal gate (HKMG) structures over a first portion of a substrate, and a third HKMG structure over a second portion of the substrate; an inter-layer dielectric (ILD) over a portion of the substrate and on sidewalls of the first, second and third HKMG structures; a spacer liner on sidewalls of the ILD between the second and third HKMG structures; and a buried contact layer between the spacer liner and in a portion of the substrate.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: September 8, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Chanro Park, Andre Labonte, Daniel Chanemougame
  • Line end structures for semiconductor devices
    Patent number: 10770392
    Abstract: A method of fabricating a semiconductor device structure comprising depositing a layer of material on a dielectric stack and patterning the layer of material to form a hard mask, depositing a metal layer covering the hard mask to form a metal hard mask, forming vias in the dielectric stack using the metal hard mask, removing the metal hard mask, and forming trenches in the dielectric stack using the hard mask, wherein the hard mask and the metal hard mask are used to define a line end structure separating the trenches.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: September 8, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Nicholas V. Licausi, Shao Beng Law
  • Chamferless interconnect vias of semiconductor devices
    Patent number: 10770344
    Abstract: A method of fabricating interconnects in a semiconductor device is provided, which includes forming an interconnect layer having a conductive line and depositing a first aluminum-containing layer over the interconnect layer. A dielectric layer is deposited over the first aluminum-containing layer, followed by a second aluminum-containing layer deposited over the dielectric layer. A via opening is formed in the second aluminum-containing layer through to the conductive line, wherein the via opening has chamferless sidewalls.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: September 8, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Yuping Ren, Haigou Huang, Ravi Prakash Srivastava, Zhiguo Sun, Qiang Fang, Cheng Xu, Guoxiang Ning
  • Micro-LED display assembly
    Patent number: 10770440
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a micro-light emitting diode (LED) display assembly and methods of manufacture. The structure includes an interposer and a plurality of micro-LED arrays each of which include a plurality of through-vias connecting pixels of the plurality of micro-LED arrays to the interposer.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: September 8, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Luke England, Bartlomiej Jan Pawlak