Patents Assigned to GLOBALFOUNDRIES Singapore Pte. Ltd.
  • Power trench capacitor compatible with deep trench isolation process
    Patent number: 10355072
    Abstract: A method for forming a trench capacitor without an additional mask adder and the resulting device are provided. Embodiments include forming a buried implant layer over a substrate; forming an EPI layer over the buried implant layer; forming an oxide layer over the EPI layer; forming a nitride layer over the oxide layer; forming first and second trenches in the nitride layer, the oxide layer, the EPI layer, the buried implant layer and the substrate, the first trench being wider and deeper than the second trench; forming a dielectric layer in the trenches; forming a first polysilicon layer over the dielectric layer in the trenches; removing the first polysilicon layer and the dielectric layer above the EPI layer in the trenches and at a bottom of the first trench; and forming a second polysilicon layer filling the first trench and above the EPI layer in the second trench.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: July 16, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Zeng Wang, Wei Si, Jeoung Mo Koo, Purakh Raj Verma
  • Split gate non-volatile memory (NVM) with improved programming efficiency
    Patent number: 10347773
    Abstract: Device and method of forming a non-volatile memory (NVM) device are disclosed. The NVM device includes NVM cells disposed on a substrate in a device region. The NVM cell includes a floating gate (FG) with first and second FG sidewalls disposed on the substrate and an intergate dielectric layer disposed over the FG and substrate. Re-entrants are disposed at corners of the intergate dielectric which are filled by dielectric re-entrant spacers. An access gate (AG) with first and second AG sidewalls is disposed on the substrate adjacent to the FG such that the second AG sidewall is adjacent to a first FG sidewall and separated by the intergate dielectric layer and the re-entrant spacers prevent AG from filling the re-entrants. A first source/drain (S/D) region is disposed in the substrate adjacent to the first AG sidewall and a second S/D region is disposed in the substrate adjacent to the second FG sidewall.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: July 9, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wei Si, Zeng Wang, Jeoung Mo Koo, Raj Verma Purakh
  • STT-MRAM flip-chip magnetic shielding and method for producing the same
    Patent number: 10347826
    Abstract: Methods of magnetically shielding a perpendicular STT-MRAM structure on all six sides within a flip-chip package and the resulting devices are provided. Embodiments include forming a passivation stack over an upper surface of a wafer and outer portions of an Al pad; forming a polymer layer over the passivation stack; forming a UBM layer over the Al pad, portions of the polymer layer and along sidewalls of the polymer layer; forming a T-shaped Cu pillar over the UBM layer; forming a ?-bump over the T-shaped Cu pillar; dicing the wafer into a plurality of dies; forming an epoxy layer over a bottom surface of each die; forming a magnetic shielding layer over the epoxy layer and along sidewalls of each die, the epoxy layer, the passivation stack and the polymer layer; and connecting the ?-bump to a package substrate with a BGA balls.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: July 9, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Bharat Bhushan, Juan Boon Tan, Danny Pak-Chum Shum, Wanbing Yi
  • Thin film resistor methods of making contacts
    Patent number: 10347710
    Abstract: A method for forming a thin film resistor (TFR) without via penetration and the resulting device are provided. Embodiments include forming a first ILD over a substrate; forming a second ILD over the first ILD; forming a first metal layer in the second ILD; forming a first nitride layer over the second ILD and the first metal layer; forming a third ILD over the first nitride layer; forming vias through the third ILD and the first nitride layer, coupled to the first metal layer; forming a TFR layer over two of the vias and the third ILD between the two vias; forming a second nitride layer over the TFR layer and the third ILD; forming a fourth ILD over the second nitride layer; and forming a second metal layer in the fourth ILD and the second nitride layer.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: July 9, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Purakh Raj Verma, Kemao Lin
  • ESD protection circuit and method of making the same
    Patent number: 10340266
    Abstract: Methods of forming a high voltage ESD GGNMOS using embedded gradual PN junction in the source region and the resulting devices are provided. Embodiments include a device having a substrate including a device region with an ESD protection circuit; a gate over the device region; a source region in the device region having a N+ implant and a P+ implant laterally separated on a first side of the gate; and a drain region in the device region on a second side of the gate, opposite the first.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: July 2, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yohann Frederic Michel Solaro, Chai Ean Gill, Tsung-Che Tsai
  • Methods for fabricating electronic devices including substantially hermetically sealed cavities and getter films
    Patent number: 10336608
    Abstract: Electronic devices and methods for fabricating electronic devices are provided. In one example, an electronic device includes an electronic device body structure having a substantially hermetically sealed cavity formed therein. A getter film is in fluid communication with the substantially hermetically sealed cavity. Conductive features are accessible from outside the substantially hermetically sealed cavity and are operatively coupled to the getter film for electrical communication with the getter film.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: July 2, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Szu Huat Goh, Edy Susanto, Jeffrey Lam
  • Floating gate OTP/MTP structure and method for producing the same
    Patent number: 10332597
    Abstract: A method of forming a FG OTP/MTP cell with a P+ drain junction at the NCAP region and the resulting device are provided. Embodiments include forming MVPW regions laterally separated in a p-sub; forming a MVNW region in the p-sub between the MVPW regions; forming a first RX, a second RX, and a third RX in the MVPW and MVNW regions, respectively; forming a first and a second pair of floating gates separated over and perpendicular to the first and second RX and the second and third RX, respectively; forming a N+ source region between and adjacent to each FG of the first and the second pair in the second RX; and forming a pair of P+ drain regions in the second RX, each P+ drain region adjacent to a FG of the first pair and a FG of the second pair and remote from the N+ source region.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: June 25, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Shyue Seng Tan, Danny Pak-Chum Shum, Eng Huat Toh
  • Resistive memory device
    Patent number: 10333065
    Abstract: A non-volatile memory device and a manufacturing method thereof are provided. The memory device includes a substrate, a lower cell dielectric layer with gate conductors and a body unit conductor disposed on the lower cell dielectric layer and gates. Memory element conductors are disposed on the body unit and lower cell dielectric layer. An upper cell dielectric layer may be on the substrate and over the lower cell dielectric layer, body unit conductor and memory element conductors. The upper cell dielectric layer isolates the memory element conductors.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: June 25, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Shyue Seng Tan, Eng Huat Toh, Xuan Anh Tran, Yuan Sun, Elgin Kiok Boone Quek
  • Hall element for 3-D sensing and method for producing the same
    Patent number: 10333056
    Abstract: A method of forming a 3D Hall effect sensor and the resulting device are provided. Embodiments include forming a p-type well in a substrate; forming a first n-type well in a first region surrounded by the p-type well in top view; forming a second n-type well in a second region surrounding the p-type well; providing n-type dopant in the first and second n-type wells; and providing p-type dopant in the p-type well and the first n-type well.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: June 25, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Bin Liu, Eng Huat Toh, Ruchil Kumar Jain
  • Poly finger fabrication for HCI degradation improvement of ultra-low-Ron EDNMOS
    Patent number: 10319834
    Abstract: Methods of forming an EDNMOS with polysilicon fingers between a gate and a nitride spacer and the resulting devices are provided. Embodiments include forming a polysilicon layer upon a GOX layer over a substrate; forming a gate and plurality of fingers and a gate and plurality of fingers through the polysilicon layer down the GOX layer; forming an oxide layer over the GOX layer and sidewalls of the gates and fingers; forming a nitride layer over the oxide layer; removing portions of the nitride and oxide layers down to the polysilicon and GOX layers to form nitride spacers; and forming S/D regions laterally separated in the substrate, each S/D region adjacent to a nitride spacer.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: June 11, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Lin Wei, Upinder Singh, Raj Verma Purakh
  • Non-volatile memory devices, RRAM devices and methods for fabricating RRAM devices with magnesium oxide insulator layers
    Patent number: 10312442
    Abstract: Non-volatile memory (NVM) devices, resistive random access memory (RRAM) devices and methods for fabricating such devices are provided. In an exemplary embodiment, a non-volatile memory (NVM) device includes a first electrode and a second electrode positioned above the first electrode. Further, the NVM device includes a variable resistance material layer positioned between the first electrode and the second electrode. The variable resistance material layer contains magnesium oxide.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: June 4, 2019
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Danny Pak-Chum Shum, Desmond Jia Jun Loy, Wen Siang Lew
  • Wafer level packaging for MEMS device
    Patent number: 10301171
    Abstract: A microelectromechanical system (MEMS) device is disclosed. The MEMS device includes a device substrate with a top device surface and a bottom device surface having a MEMS component in a device region. A top device bond ring is disposed on the top device surface surrounding the device region and a bottom device bond ring is disposed on the bottom device surface surrounding the device region. A top cap with a top cap bond ring is bonded to the top device bond ring by a top eutectic bond and a bottom cap with a bottom cap bond ring is bonded to the bottom device bond ring by a bottom eutectic bond. The eutectic bonds encapsulate the MEMS device.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: May 28, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Siddharth Chakravarty, Pradeep Yelehanka, Sharath Poikayil Poikayil Satheesh, Chun Hoe Yik, Rakesh Kumar, Natarajan Rajasekaran
  • Composite spacer layer for magnetoresistive memory
    Patent number: 10297745
    Abstract: A bottom pinned perpendicular magnetic tunnel junction (pMTJ) with high TMR which can withstand high temperature back-end-of-line (BEOL) processing is disclosed. The pMTJ includes a composite spacer layer between a SAF layer and a reference layer of the fixed magnetic layer of the pMTJ. The composite spacer layer includes a first non-magnetic (NM) spacer layer, a magnetic (M) spacer layer disposed over the first NM spacer layer and a second NM spacer layer disposed over the M layer. The M layer is a magnetically continuous amorphous layer, which provides a good template for the reference layer.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: May 21, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Taiebeh Tahmasebi, Vinayak Bharat Naik, Kangho Lee, Chim Seng Seet, Kazutaka Yamane
  • Integrated LED and LED driver units and methods for fabricating the same
    Patent number: 10297711
    Abstract: Integrated LED and LED driver units and methods for fabricating integrated LED and LED driver units and products with a plurality of integrated LED and LED driver units are provided. In an embodiment, a method for fabricating an integrated LED and LED driver includes forming an LED driver in a first substrate, wherein the first substrate is a semiconductor substrate. The method include forming a bond pad over a top surface of the semiconductor substrate and electrically connected to the LED driver. Also, the method includes forming an LED on a second substrate. Further, the method includes directly coupling the LED to the bond pad.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: May 21, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventor: Donald R. Disney
  • Integrated circuit electrostatic discharge protection
    Patent number: 10298215
    Abstract: Integrated circuits (ICs) include electrostatic discharge protection including a transistor having a drain operably coupled to a first rail of the integrated circuit and a source operatively coupled to a second rail of the integrated circuit. A voltage regulating trigger circuit is operatively coupled to the first rail and to a gate of the transistor to turn on of the transistor responsive to an ESD event affecting the integrated circuit, wherein the voltage regulating trigger circuit limits a potential of the first rail to a first potential and a gate potential of the transistor to a second potential, less than the first potential but sufficient to turn the transistor on to conduct current arising from the ESD event from the first rail to the second rail.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: May 21, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wei Gao, Yi Lu, Handoko Linewih
  • High-Density STT-MRAM with 3D arrays of MTJs in multiple levels of interconnects and method for producing the same
    Patent number: 10290679
    Abstract: A scalable method of forming an integrated high-density STT-MRAM with a 3D array of multi-level MTJs and the resulting devices are provided. Embodiments include providing a Si substrate of an X-density STT-MRAM having an array of interconnect stacks; forming a level of a MTJ structure on each of a first interconnect stack and a second interconnect stack, wherein (X?1) defines a number of interconnect stacks between the first and the second interconnect stacks; forming a via on each interconnect stack without a MTJ structure; forming a metal layer on each MTJ structure and via on the level; repeating the forming of the MTJ structure, the via, and the metal layer one interconnect stack laterally shifted until the level of the MTJ structure equals X, only forming the MTJ structure at that level; forming a bit line over the substrate; and connecting the bit line to each MTJ structure.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: May 14, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Bharat Bhushan, Juan Boon Tan, Yi Jiang, Danny Pak-Chum Shum, Wanbing Yi
  • Magnetic shielding package structure for MRAM device and method for producing the same
    Patent number: 10290678
    Abstract: Methods of magnetically shielding an MRAM structure on all six sides in a thin wire or thin flip chip bonding package and the resulting devices are provided. Embodiments include forming a first metal layer embedded between an upper and a lower portion of a PCB substrate, the first metal layer having a pair of metal filled vias laterally separated; attaching a semiconductor die to the upper portion of the PCB substrate between the pair of metal filled vias; connecting the semiconductor die electrically to the PCB substrate through the pair of metal filled vias; removing a portion of the upper portion of the PCB substrate outside of the pair of metal filled vias down to the first metal layer; and forming a second metal layer over and on four opposing sides of the semiconductor die, the second metal layer landed on the first metal layer.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: May 14, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Shan Gao, Boo Yang Jung
  • MTJ structures, STT MRAM structures, and methods for fabricating integrated circuits including the same
    Patent number: 10283246
    Abstract: Magnetic tunnel junction (MTJ) structures, spin transfer torque magnetic random access memory (STT MRAM) structures, and methods for fabricating integrated circuits including such structures are provided. In an embodiment, an MTJ structure includes a cobalt iron carbon (CoFeC) fixed reference layer. Further, the MTJ structure includes a cobalt iron carbon (CoFeC) free storage layer. Also, the MTJ structure includes a tunnel barrier layer between the fixed reference layer and the free storage layer.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: May 7, 2019
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Danny PakChum Shum, Francis YongWee Poh, Jingsheng Chen, Shaohai Chen
  • Extended drain transistor on a crystalline-on-insulator substrate
    Patent number: 10283622
    Abstract: A high voltage (HV) transistor is integrated on a silicon-on-insulator (SOI) substrate. The HV transistor is disposed in a HV device region disposed on a bulk substrate of the SOI substrate. The HV device region includes a top field oxide which includes at least a part of a buried oxide (BOX) of the SOI substrate. A HV gate is disposed in HV region overlapping the HV top field oxide and includes first and second HV gate sidewalls. A drain is disposed on the bulk substrate and displaced from the first HV gate sidewall by the HV top field oxide. A source is disposed on the bulk substrate adjacent to the side of the second HV gate sidewall.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: May 7, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventor: Guowei Zhang
  • High coupling ratio split gate memory cell
    Patent number: 10276582
    Abstract: A split gate non-volatile memory (NVM) cell formed on a crystalline-on-insulator (COI) substrate, such as a fully or partially depleted silicon-on-insulator (SOI) substrate is disclosed. The split gate memory cell includes a split gate disposed on a surface substrate of the SOI substrate between source/drain (S/D) regions. The split gate includes a storage gate with a control gate (CG) over a floating gate (FG), and a select gate (SG). A back gate is provided on the bulk substrate below a buried oxide (BOX). The back gate may be doped with the same polarity type dopants as the S/D regions. The back gate is coupled to the CG to increase CG coupling ratio, improving programming performance. Alternatively, the back gate may be doped with the opposite polarity type dopants as the S/D regions. The back gate is coupled to a negative bias during program and erase operations.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: April 30, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yuan Sun, Shyue Seng Tan, Eng Huat Toh