Abstract: Methods of designing a BAW resonator having fractal geometry and the resulting devices are provided. Embodiments include providing a fractal generator function; providing three or more line segments; applying the fractal generator function to each of the three or more line segments to form three or more respective fractal line segments, each of the three or more fractal line segments having a respective start point and endpoint and at least four sub-segments; and connecting an endpoint of each one of the three or more fractal line segments to a successive start point of another of the three or more fractal line segments to form a closed-loop contour line representative of an area of an electrode of a BAW resonator, the closed-loop contour line having a fractal dimension that is greater than one and less than two.

Abstract: A method of forming a uniform self-aligned low-k layer with a large process window for inserting a memory array with pillar/convex topography and the resulting device are provided. Embodiments include forming a substrate with a first region and a second region; forming a first low-K layer over the substrate; forming an oxide layer over the first low-K layer; forming a spacer over the oxide layer; etching the spacer to expose the oxide layer in the first region; removing the oxide layer and a portion of the first low-K layer in the first region and a portion of the oxide layer and a portion of the spacer in the second region; removing the spacer in the second region; cleaning the first low-K layer and the oxide layer, a triangular-like shaped portion of the oxide layer remaining; and forming a second low-K layer over the substrate.

Abstract: Spin transfer torque magnetic random access memory structures, integrated circuits, and methods for fabricating integrated circuits and/or memory cells are provided. An exemplary method for fabricating integrated circuit includes forming a bottom electrode and forming a fixed layer disposed over the bottom electrode. The fixed layer includes a hard layer disposed over a base layer. The base layer includes a seed layer of nickel (Ni) and chromium (Cr) and has a thickness of less than about 100 Angstrom (A). The method further includes forming at least a first tunnel barrier layer over the hard layer, forming a storage layer over the first tunnel barrier layer, and forming a top electrode over the storage layer.

Abstract: High density resistive memory structures, integrate circuits with high density resistive memory structures, and methods for fabricating high density resistive memory structures are provided. In an embodiment, a high density resistive memory structure includes a semiconductor substrate and a plurality of first electrodes in a first plane in and/or over the semiconductor substrate. Further, the high density resistive memory structure includes a plurality of second electrodes in a second plane in and/or over the semiconductor substrate. The second plane is parallel to the first plane, and each second electrode in the plurality of second electrodes crosses over or under each first electrode in the plurality of first electrodes at a series of cross points. Each second electrode in the plurality of second electrodes is non-linear and the series of cross points formed by each respective second electrode is non-linear.

Abstract: Semiconductor memory devices and methods for writing data in memory cells are provided. An exemplary method for writing data in a memory cell includes providing the memory cell with a first pull-up transistor, a first power supply line coupled to the first pull-up transistor, a second pull-up transistor, and a second power supply line coupled to the second pull-up transistor. The method further includes applying a primary voltage from the first power supply line to the first pull-up transistor. The method also includes applying a secondary voltage from the second power supply line to the second pull-up transistor, wherein the secondary voltage is higher than the primary voltage. Further, the method includes performing a write operation to save a selected value in the memory cell.

Abstract: A method of forming a memory device with a dielectric blocking layer and selective silicidation and the resulting device are provided. Embodiments include forming a memory stack on a substrate; forming a conformal insulating layer over sidewalls and an upper surface of the memory stack and the substrate; forming an interpoly dielectric structure adjacent to each sidewall of the insulating layer; forming a conformal polysilicon silicon layer over the insulating layer and interpoly dielectric structures; forming an optical planarization layer over the polysilicon layer; planarizing the optical planarization and polysilicon layers down to the memory stack; forming a dielectric blocking layer over the memory stack and substrate; forming a patterning stack over the dielectric blocking layer, the patterning stack covering a portion of the memory stack; and removing the dielectric blocking, optical planarization, and polysilicon layers on opposite sides of the patterning stack.

Abstract: A method of forming a bulk transistor integrated with silicon-on-insulator (SOI) field plates, and related device, are provided. Embodiments include forming a silicon-on-insulator (SOI) substrate as a field plate on a field plate oxide; forming a high-voltage p-type well in a p-type substrate of a bulk transistor on which the SOI substrate is formed, the high-voltage p-type formed between shallow trench isolation (STI) region of the p-type substrate; forming an n-drift region in the high-voltage p-type well; forming a first gate on the high-voltage p-type well; and implanting a first n-type region adjacent to the gate as a source region and a second n-type region adjacent to the SOI substrate as a drain region.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a capacitor, where the capacitor includes a first capacitor plate and a second capacitor plate. The first capacitor plate includes a first memory cell, and the second capacitor plate includes a second memory cell. The capacitor is utilized as a functional capacitor in the integrated circuit.

Abstract: A method of forming a 3D Hall effect sensor and the resulting device are provided. Embodiments include forming a p-type well in a substrate; forming a first n-type well in a first region surrounded by the p-type well in top view; forming a second n-type well in a second region surrounding the p-type well; implanting n-type dopant in the first and second n-type wells; and implanting p-type dopant in the p-type well and the first n-type well.

Abstract: LDMOS transistor structures and integrated circuits including LDMOS transistor structures are provided. An exemplary integrated circuit including an LDMOS transistor structure includes a substrate including a first region and a second region. The substrate includes a bulk layer and, in the second region, an insulator layer overlying the bulk layer and a semiconductor layer overlying the insulator layer. The integrated circuit further includes a gate structure overlying the semiconductor layer. A channel region is formed in the semiconductor layer under the gate structure. The integrated circuit also includes a well contact region on the bulk layer in the first region, a source region overlying the substrate, and a drain region overlying the substrate. A drift region is located between the drain region and the gate structure.

Abstract: Integrated circuits including tunnel transistors and methods for fabricating such integrated circuits are provided. An exemplary method for fabricating an integrated device includes forming a lower source/drain region in and/or over a semiconductor substrate. The method forms a channel region overlying the lower source/drain region. The method also forms an upper source/drain region overlying the channel region. The method includes forming a gate structure beside the channel region.

Abstract: Devices and methods for forming a device are disclosed. A substrate is provided. A plurality of fin structures are formed in the substrate. The fin structures include an upper part and a lower part. An isolation layer is formed on the substrate. The lower part of the plurality of fin structures is embedded in the isolation layer. A source including a first source portion and a second source portion is formed in a first side of the substrate. The first source portion partially occupies the fin structures along a length direction. The second source portion is formed over the first source portion. The second source portion elevates the fin structures. A drain is formed in a second side of the substrate. A distance between the source to the drain defines a channel region. A gate having a gate dielectric and a metal gate electrode is formed over the substrate. The gate wraps around the elevated fin structures and channel region.

Abstract: A device and a method for forming a device are disclosed. The method includes providing a substrate prepared with a device region. A device well having second polarity type dopants is formed in the substrate. A threshold voltage (VT) implant is performed with a desired level of second polarity type dopants into the substrate. The VT implant forms a VT adjust region to obtain a desired VT of a transistor. A co-implantation with diffusion suppression material is performed to form a diffusion suppression (DS) region in the substrate. The DS region reduces or prevents segregation and out-diffusion of the VT implanted second polarity type dopants. A transistor of a first polarity type having a gate is formed in the device region. First and second diffusion regions are formed adjacent to sidewalls of the gate.

Abstract: A device and methods of forming the device are disclosed. A substrate with a circuits component and a dielectric layer with interconnects is provided. A pad level dielectric layer is formed over the dielectric layer. A primary passivation layer is formed over the pad level dielectric layer with pad interconnects. The substrate is subjected to an alloying process. During the alloying process, the primary passivation layer prevents or reduces formation of hillocks on surfaces of the pad interconnects to improve surface smoothness of the pad interconnects. Pad openings are formed in the pad level dielectric layer to expose top surfaces of the pad interconnects. A cap dielectric layer is formed on the substrate and lines the primary passivation layer as well as the exposed top surfaces of the pad interconnects. A final passivation layer is formed on the substrate and covers the cap dielectric layer. The final passivation layer is patterned to form final passivation openings corresponding to the pad openings.

Abstract: Device and methods of forming a device are disclosed. The method includes providing a substrate defined with at least first and second regions. A first dielectric layer is provided over the first and second regions of the substrate. The first dielectric layer corresponds to pre-metal dielectric (PMD) or CA level which comprises a plurality of contact plugs in the first and second regions. A first interlevel dielectric (ILD) layer is provided over the first dielectric layer. The first ILD layer accommodates a plurality of metal lines in M1 metal level in the first and second regions and via contact in V0 via level in the first region. A magnetic random access memory (MRAM) cell is formed in the second region. The MRAM cell includes a magnetic tunnel junction (MTJ) element sandwiched between the M1 metal level and CA level.

Abstract: A metal oxide semiconductor varactor includes an active area doped well that is disposed within a semiconductor substrate and a gate structure including a first portion that extends over the active area doped well and a second portion that extends over the semiconductor substrate outside of the active area doped well. The varactor further includes at least one active area contact structure formed in physical and electrical connection with the active area doped well, in a three-sided contact-landing area of the active area doped well. Still further, the varactor includes a gate contact structure that is formed in physical and electrical contact with the gate structure in the second portion of the gate structure such that the gate contact structure overlies the semiconductor substrate outside of the active area doped well.

Abstract: Devices and methods for forming a device are presented. The method for forming the device includes providing a support substrate having first crystal orientation. A trap rich layer is formed on the support substrate. An insulator layer is formed over a top surface of the trap rich layer. The method further includes forming a top surface layer having second crystal orientation on the insulator layer. The support substrate, the trap rich layer, the insulator layer and the top surface layer correspond to a substrate and the substrate is defined with at least first and second device regions. A transistor is formed in the top surface layer in the first device region and a wide band gap device is formed in the second device region.

Abstract: An integrated monolithic device with a micro-electromechanical system (MEMS) and an integrated circuit (IC) and a method of forming thereof is disclosed. The monolithic device includes a substrate with IC components and a MEMS formed over the IC. A back-end-of-line (BEOL) dielectric having IC interconnect pads in a pad level is formed over the substrate. A MEMS is formed over the BEOL dielectric with the IC interconnect pads. The MEMS includes a MEMS stack having an active MEMS layer and patterned top and bottom MEMS electrodes formed on the top and bottom surfaces of the active MEMS layer. IC MEMS contact vias are formed at least partially through the active MEMS layer. IC MEMS contacts are formed in the IC MEMS contact vias in the active MEMS layer and configured to couple to the IC interconnect pads.

Abstract: Three-axis monolithic microelectromechanical system (MEMS) accelerometers and methods for fabricating integrated capacitive and piezo accelerometers are provided. In an embodiment, a three-axis MEMS accelerometer includes a first sensing structure for sensing acceleration in a first direction. Further, the three-axis MEMS accelerometer includes a second sensing structure for sensing acceleration in a second direction perpendicular to the first direction. Also, the three-axis MEMS accelerometer includes a third sensing structure for sensing acceleration in a third direction perpendicular to the first direction and perpendicular to the second direction. At least one sensing structure is a capacitive structure and at least one sensing structure is a piezo structure.

Abstract: Devices and methods for manufacturing a device are presented. The device includes a substrate and a vertical structure disposed over the substrate. The vertical structure includes one or more memory cell stacks with a dielectric layer between every two adjacent cell stacks. Each of the one or more cell stacks includes first and second first type conductors on first and second sides of the cell stack, respectively; first and second electrodes, the first electrode adjacent the first first type conductor, the second electrode adjacent the second first type conductor; and first and second memory elements, the first memory element disposed between the first first type conductor and the first electrode, the second memory element disposed between the second first type conductor and the second electrode. The device also includes a selector element disposed over the substrate and vertically traversing through a middle portion of the vertical structure.