Abstract: Methods of forming a high sensitivity Hall effect sensor having a thin Hall plate and the resulting devices are provided. Embodiments include providing a SOI substrate having a sequentially formed Si substrate and BOX and Si layers; forming a first STI structure in a first portion of the Si layer above the BOX layer, the first STI structure having a cross-shaped pattern; forming a second STI structure in a frame-shaped pattern in a second portion of the Si layer; the second STI structure formed outside and adjacent to the first STI structure; removing a portion of the Si layer between the first and second STI structures down to the BOX layer; removing the first STI structure, a cross-shaped Si layer remaining; and implanting N+ dopant ions into each end of the cross-shaped Si layer to form N+ implantation regions.

Abstract: Methods to forming low trigger-voltage ESD protection circuit in FinFET IC devices and resulting devices. Embodiments include providing a substrate including a first-type well area in an ESD region; forming a base junction of the first-type along the perimeter of the ESD region; forming a shallow trench isolation (STI) region adjacent the base junction; forming alternate emitter and collector junctions of a second-type adjacent the STI region, parallel to and spaced from each other by parallel additional STI regions; forming at least one gate perpendicular to and over a collector junction; and forming a floating ESD nodes of the first-type in the collector junction adjacent one side of the at least one gate.

Abstract: Methods of forming a compact FinFET OTP/MTP cell and a compact FDSOI OTP/MTP cell and resulting devices are provided. Embodiments include providing a substrate having a BOX layer; forming fins on the BOX layer with a gap in between; forming first and second gates, laterally separated, over and perpendicular to the fins; forming at least one third gate between the first and second gates and contacting the BOX layer through the gap, each third gate overlapping an end of a fin or both fins; forming a S/D region in each of the fins adjacent to the first and second gates, respectively, remote from the at least one third gate; utilizing each of the first and second gates as a WL; utilizing each third gate as a SL or connecting a SL to the S/D region; and connecting a BL to the S/D region or the at least one third gate.

Abstract: A method of forming a stop layer to prevent dummy vias from connecting to a metal layer and the resulting device are provided. Embodiments include forming a first metal layer in a first dielectric layer; forming a second dielectric layer over a first Nblok layer formed over the first dielectric and first metal layers; forming a third dielectric layer over the second dielectric layer and a second Nblok layer formed over a portion of the second dielectric layer; forming a via and a plurality of vias through the third and second dielectric layers down to the second and first Nblok layers, respectively; removing portions of the second and first Nblok layers through the via and the plurality of vias down to the second dielectric layer and the first metal layer, respectively; removing portions of the third dielectric layer through each via; and filling each via with a second metal layer.

Abstract: Memory devices and manufacturing methods thereof are presented. A memory device a substrate and a memory cell having at least one selector and a storage element. The selector includes a well of a first polarity type disposed in the substrate, a region of a second polarity type disposed over the well and in the substrate, and first and second regions of the first polarity type disposed adjacent to the region of the second polarity type. The storage element includes a programmable resistive layer disposed on the region of the second polarity type and an electrode disposed over the programmable resistive layer.

Abstract: Methods for preventing step-height difference of flash and logic gates in FinFET devices and related devices are provided. Embodiments include forming fins in flash and logic regions; recessing an oxide exposing an upper portion of the fins; forming an oxide liner over the upper portion in the flash region; forming a polysilicon gate over and perpendicular to the fins in both regions; removing the gate from the logic region and patterning the gate in the flash region forming a separate gate over each fin; forming an ONO layer over the gates in the flash region; forming a second polysilicon gate over and perpendicular to the fins in both regions; planarizing the second polysilicon gate exposing a portion of the ONO layer over the gates in the flash region; forming and patterning a hardmask, exposing STI regions between the flash and logic regions; and forming an ILD over the STI regions.

Abstract: Methods of fabricating a flexible dummy fill to increase MTJ density are provided. Embodiments include forming a first oxide layer; forming lower interconnect layers in the first oxide layer; forming a nitride layer over the first oxide layer and the lower interconnect layers; forming a second oxide layer over the nitride layer; forming bottom electrodes through the second oxide layer and the nitride layer contacting a portion of an upper surface of the lower interconnect layers; forming MTJ structures over the bottom electrodes; forming top electrodes over the MTJ structures; and forming upper interconnect layers over one or more of the top electrodes.

Abstract: A compact and reliable changeable negative voltage transmission circuit is described. It is very useful for applications need passing changeable negative voltage to selected pins in certain mode. The changeable negative voltage is 0V when enable signal EN is low and ?V1 when enable signal EN is high. The circuit includes a control circuit and an output circuit. The control circuit includes a control high power source VDD and a control low power source VNEG. The control circuit generates control output signals CON and CON_B to the output circuit to output either 0V if IN is low or ?V1 if IN is high when EN is high. Only single type VT transistor is used in the transmission circuit without any reliability concern, no extra bias voltage is need, which reduces the area and keeps the manufacturing cost low.

Abstract: High voltage devices and methods for forming a high voltage device are disclosed. The method includes providing a substrate having top and bottom surfaces. The substrate is defined with a device region and a recessed region disposed within the device region. The recessed region includes a recessed surface disposed lower than the top surface of the substrate. A transistor is formed over the substrate. Forming the transistor includes forming a gate at least over the recessed surface and forming a source region adjacent to a first side of the gate below the recessed surface. Forming the transistor also includes forming a drain region displaced away from a second side of the gate. First and second device wells are formed in the substrate within the device region. The first device well encompasses the drain region and the second device well encompasses the source region.

Abstract: Memory cells and methods for forming a memory cell are disclosed. The memory cell includes a first selector having a first gate coupled to a first word line (WL) and first and second source/drain (S/D) regions, and a second selector having a second gate coupled to a second WL and first and second S/D regions. The second S/D regions of the first and the second selectors are a common S/D region. The first and the second WLs are a common WL and the second S/D regions of the first and second selectors are coupled to a source line (SL). The memory cell includes a storage element which includes a magnetic tunnel junction (MTJ) element coupled with a bit line (BL) and the first and the second selectors, and a voltage control switch which includes a metal-insulator-transition (MIT) material coupled with the first selector.

Abstract: Devices and methods for forming a device are disclosed. At least one die is provided. A redistribution layer having a fan-out region extends concentrically outwards from an outer perimeter of the at least one die. A seal ring is disposed in the fan-out region of the redistribution layer.

Abstract: Memory cells and method of forming thereof are presented. The method includes forming a magnetic tunnel junction (MTJ) element which includes a fixed magnetic layer, a tunneling barrier layer and a composite free magnetic layer. The composite free magnetic layer includes an insertion layer between first and second free magnetic layers. The insertion layer includes an oxide or oxidized layer. The insertion layer increases the overall thickness of the free layer, decreasing switching current as well as thermal stability. The oxidized layer may be MgO or HfOx. A surface layer may be provided over the oxide or oxidized layer to further enhance magnetic anisotropy to further decrease switching current. The surface layer is Ta, Ti or Hf.

Abstract: A method of forming a segmented FDSOI STT-MRAM using dummy WL blocks and the resulting device are provided. Embodiments include forming a plurality of FDSOI STT-MRAM active WL blocks laterally separated across a memory array; forming a FDSOI STT-MRAM dummy WL block parallel to and on opposite sides of each active WL block; forming a plurality of SL structures laterally separated across the memory array; forming a plurality of BL structures laterally separated across the memory array; and connecting the plurality of SL and BL structures to the plurality of active WL blocks.

Abstract: A seal ring structure is disclosed for integrated circuit (IC) packaging. The seal ring includes an inner moisture barrier ring and an outer crack stop ring. Line structures of both the inner and outer rings include chamfered corners. The chamfers of a chamfered corner are devoid of acute angles. No metal line structure for the inner ring is provided at the pad level. The seal ring as described improves the reliability and strength of the structure and hence the seal ring can sustain high stress at the corners of the die during dicing.

Abstract: Integrated circuits and methods of producing integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a source and a drain defined within a body isolation well. A gate overlies the body isolation well between the source and the drain, and an isolating structure is formed within the body isolation well. The isolating structure sections the source into a plurality of source sections with the plurality of source sections adjacent to one gate.

Abstract: Integrating magnetic random access memory with logic is disclosed. The magnetic tunnel junction stack of a magnetic memory cell is disposed within a dielectric layer which serves as a via level of an interlevel dielectric layer with a metal level above the via level. An integration scheme for forming dual damascene structures for interconnects can be formed to logic and memory cells easily.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate with a handle layer, a buried insulator layer overlying the handle layer, and an active layer overlying the buried insulator layer. The handle layer and the active layer include monocrystalline silicon. A transistor overlies the buried insulator layer, and a solar cell is within the handle layer such that the buried insulator layer is between the solar cell and the transistor. The solar cell includes a solar cell outer layer in electrical communication with a solar cell outer layer contact, and a solar cell inner layer in electrical communication with a solar cell inner layer contact. The solar cell inner and outer layers are monocrystalline silicon.

Abstract: Embodiments of a method of processing semiconductor devices are presented. The method includes providing a substrate prepared with isolation regions having a non-planar surface topology. The substrate includes at least first and second regions. The first region includes a memory region and the second region includes a logic region. A hard mask layer is formed covering the substrate and the isolation regions with non-planar surface topology. The method includes selectively processing an exposed portion of the hard mask layer over a select region while protecting a portion of the hard mask layer over a non-select region. The top substrate area and isolation regions of the non-select region are not exposed during processing of the portion of the hard mask layer over the select region. Hard mask residue is completely removed over the select region during processing of the exposed portion of the hard mask layer.

Abstract: Integrated circuits including semiconductor memory devices, read assist circuits for semiconductor memory devices, and methods for operating such circuits are provided. In an embodiment, a read assist circuit for use in a semiconductor memory device is provided. The read assist circuit includes a first drive device for driving a wordline of the semiconductor memory device to a wordline driving voltage. The first drive device operates at a first current. The read assist circuit also includes a second drive device for maintaining the wordline of the semiconductor memory device at the wordline driving voltage. The second drive device operates at a second current lower than the first current.

Abstract: A semiconductor device with embedded non-volatile memory (eNVM) is described. The device is formed on a silicon-on-insulator (SOI) substrate, such as a fully depleted SOI (FDSOI) substrate. The substrate includes a SOI region and a hybrid region. The SOI region includes the surface substrate, BOX and bulk substrate while the hybrid region includes only the bulk substrate. NVM and high voltage (HV) transistors are disposed in the hybrid region while a logic and radio frequency (RF) transistors are disposed in the SOI region. The gates of the various transistors have about coplanar top surfaces. As such, the hybrid region compensates for height differential of transistors, enabling transistors to have about coplanar top surfaces. In addition, the hybrid region enables transistors which suffer from floating body effects to be disposed therein.