Abstract: A device may include a semiconductor-on-insulator (SOI) structure that may include a substrate, an insulator layer over the substrate, and a semiconductor layer over the insulator layer. The semiconductor layer may include a first conductivity region and a second conductivity region at least partially arranged within the semiconductor layer. The device may further include a gate structure arranged over the semiconductor layer and between the first conductivity region and the second conductivity region; a first conductor element arranged through the semiconductor layer and the insulator layer of the SOI structure to electrically contact the substrate; a second conductor element arranged to electrically contact the gate structure; and a conducting member connecting the first conductor element and the second conductor element to electrically couple the first conductor element and the second conductor element.

Abstract: A memory device may include a substrate, a first gate structure, a mask and a second gate structure. The substrate may include a source region and a drain region at least partially arranged within the substrate, and a channel region arranged between the source region and the drain region. The first gate structure may be at least partially arranged over the channel region, and may include a top surface that may be substantially flat. The mask may be at least partially arranged over the top surface of the first gate structure. The second gate structure may be at least partially arranged over the mask and at least partially arranged adjacent to the first gate structure.

Abstract: A resonator device may include a stacked first resonator and second resonator. The first resonator may be configured to resonate at a first operating frequency, and the second resonator may be configured to resonate at a second operating frequency different from the first operating frequency. The first resonator may include a first electrode and a first active layer arranged over the first electrode. The second resonator may include a second active layer arranged over the first active layer, and a second electrode arranged over the second active layer. The stacked first resonator and second resonator may be coupled to a reconfiguration switch for selectively operating at the first operating frequency or the second operating frequency. One of the first resonator and the second resonator is active upon selection by the reconfiguration switch, while the other resonator is inactive.

Abstract: Methods of forming a MTJ dummy fill gradient across near-active-MRAM-cell periphery and far-outside-MRAM logic regions and the resulting device are provided. Embodiments include providing an embedded MRAM layout with near-active-MRAM-cell periphery logic and far-outside-MRAM logic regions; forming a MTJ structure within the layout based on minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first and second metal layers; forming a high-density MTJ dummy structure in the near-active-MRAM-cell periphery logic region based on second minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer; and forming a low-density MTJ dummy structure in the far-outside-MRAM logic region based on third minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer.

Abstract: A system and method for defect localization in embedded memory are provided. Embodiments include a system including automated testing equipment (ATE) interfaced with a wafer probe including a diagnostic laser for stimulating a DUT with the diagnostic laser at a ROI. The ATE is configured to simultaneously perform a test run at a test location of the DUT with a test pattern during stimulation of the DUT. Failing compare vectors of a reference failure log of a defective device are stored. A first profile module is configured to generate a first 3D profile from each pixel of a reference image of the defective device. A second profile module is configured to generate a second 3D profile from each pixel of the ROI of the DUT. A cross-correlation module is configured to execute a pixel-by-pixel cross-correlation from the first and second 3D profiles and generate an intensity map corresponding to a level of correlation between the DUT and defective device.

Abstract: Transistor-based sensors and fabrication methods for a transistor-based sensor. A semiconductor layer is arranged over a substrate, and an interconnect structure is arranged over the semiconductor layer and the substrate. The semiconductor layer includes first sections composed of a semiconductor material, second sections composed of the semiconductor material, and cavities. The first sections have an alternating arrangement with the second sections in a lateral direction. The semiconductor material of the first sections is polycrystalline, and the semiconductor material of the second sections is single-crystal. First and second openings each extend in a vertical direction through the metallization levels of the interconnect structure to the semiconductor layer or through the substrate to the semiconductor layer. The first opening defines a first fluid inlet coupled to the cavities, and the second opening defines a first fluid outlet coupled to the cavities.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a memory cell, wherein the memory cell includes a transistor having a source and a drain, a first resistive unit in electrical communication with the source, and a second resistive unit in electrical communication with the drain. The first resistive unit includes a first bottom electrode, a first top electrode, and a first resistive element positioned between the first bottom electrode and the first top electrode. The second resistive unit includes a second bottom electrode, a second top electrode, and a second resistive element positioned between the second bottom electrode and the second top electrode.

Abstract: Laterally-diffused-metal-oxide-silicon (LDMOS) devices, integrated circuits including LDMOS devices, and methods for fabricating the same are provided. An exemplary LDMOS device includes a substrate having a surface, a gate structure overlying the surface and a channel region in the substrate below the gate structure, and a drain region in the substrate. The LDMOS device further includes a surface insulator region disposed between the gate structure and the drain region at the surface of the substrate and a dielectric block different from the surface insulator region and located over the surface insulator region. Also, the LDMOS device includes a field effect structure. The field effect structure includes a field plate disposed over and distanced from the surface of the substrate. The field effect structure also includes a conductive structure coupled to the field plate and extending from the field plate toward the dielectric block.

Abstract: An anti-fuse memory cell may include a substrate including first and second conductivity regions and an isolation region at least partially within the substrate, a program gate over the substrate, a program gate oxide layer over the isolation region and between the program gate and the substrate, a first channel region arranged laterally between the first conductivity region and the isolation region, a second channel region arranged laterally between the second conductivity region and the isolation region, a first select gate arranged over the substrate and over the first channel region and a second select gate arranged over the substrate and over the second channel region. The program gate oxide layer may be configured to break down to allow conduction between the program gate and at least one of the channel regions upon providing a program voltage difference between the program gate and at least one of the channel regions.

Abstract: A memory device may include a substrate having conductivity regions and a channel region. A first voltage line may be arranged over the channel region. A second voltage line, and third and fourth voltage lines may be electrically coupled to a first conductivity region and a second conductivity region respectively. Resistive units may be arranged between the third and fourth voltage lines and the second conductivity region. In use, changes in voltages applied between the second and third voltage lines, and between the second and fourth voltage lines may cause resistances of first and second resistive units to switch between lower and higher resistance values. The lower resistance value of the first resistive unit may be different from the lower resistance value of the second resistive unit and/or the higher resistance value of the first resistive unit may be different from the higher resistance value of the second resistive unit.

Abstract: A method for forming a trench capacitor without an additional mask adder and the resulting device are provided. Embodiments include forming a buried implant layer over a substrate; forming an EPI layer over the buried implant layer; forming an oxide layer over the EPI layer; forming a nitride layer over the oxide layer; forming first and second trenches in the nitride layer, the oxide layer, the EPI layer, the buried implant layer and the substrate, the first trench being wider and deeper than the second trench; forming a dielectric layer in the trenches; forming a first polysilicon layer over the dielectric layer in the trenches; removing the first polysilicon layer and the dielectric layer above the EPI layer in the trenches and at a bottom of the first trench; and forming a second polysilicon layer filling the first trench and above the EPI layer in the second trench.

Abstract: Structures for a sensor and fabrication methods for a sensor. Features each having a top surface and a plurality of side surfaces are formed. A sensing layer is formed on the top surface and the side surfaces of each feature, and an interconnect structure having one or more interlayer dielectric layers is formed over the features. The one or more interlayer dielectric layers include a cavity arranged to expose the sensing layer, and the sensing layer is composed of a material that is sensitive to a property of an analyte solution provided in the cavity.

Abstract: The disclosed subject matter relates to a structure and method to improve bond pad reliability of semiconductor devices. According to an aspect of the present disclosure, a bond pad structure is provided that includes a dielectric layer and at least one bond pad in the dielectric layer, wherein the bond pad has a top surface. A passivation layer has an opening over the bond pad, wherein the opening has sidewalls. A low-k barrier layer is covering the sidewalls of the opening and the top surface of the bond pad. Protective structures are formed over the sidewalls of the opening.

Abstract: According to various non-limiting embodiments a memory device may include a silicon-on-insulator layer having a conductivity of a first polarity, a first raised structure over the silicon-on-insulator layer, the second raised structure over the silicon-on-insulator layer, an dummy gate arranged between the first raised structure and the second raised structure, and a memory connected to the second raised structure. The first raised structure may have a conductivity of the first polarity, and the second raised structure may include a first diode layer having a conductivity of a second polarity opposite to the first polarity.

Abstract: An integrated wafer probe card with a light source facing a device under test (DUT) side and enabling methodology are provided.

Abstract: Structures for a non-volatile memory and methods of forming and using such structures. A resistive memory element includes a first electrode, a second electrode, and a switching layer arranged between the first electrode and the second electrode. A transistor includes a drain coupled with the second electrode. The switching layer has a top surface, and the first electrode is arranged on a first portion of the top surface of the switching layer. A hardmask, which is composed of a dielectric material, is arranged on a second portion of the top surface of the switching layer.

Abstract: Devices and methods of forming a device are disclosed. The device includes a substrate defined with at least a device region. A multi-gate transistor disposed in the device region which includes first and second gates both having first and second gate sidewalls. The multi-gate transistor also includes first source/drain (S/D) regions disposed adjacent to the first gate sidewall of the first and second gate, a common second S/D region disposed adjacent to the second gate sidewall of the first and second gate. A negative capacitance element is disposed within the second gate to reduce total overlap capacitance of the transistor. An interlevel dielectric (ILD) layer is disposed over the substrate and covering the transistor. First and second contacts are disposed in the ILD layer which are coupled to the first and second S/D regions respectively.

Abstract: Memory cells and method of forming thereof are presented. The method includes forming a magnetic tunnel junction (MTJ) element which includes a fixed magnetic layer, a tunneling barrier layer and a composite free magnetic layer. The composite free magnetic layer includes an insertion layer between first and second free magnetic layers. The insertion layer includes an oxide or oxidized layer. The insertion layer increases the overall thickness of the free layer, decreasing switching current as well as thermal stability. The oxidized layer may be MgO or HfOx. A surface layer may be provided over the oxide or oxidized layer to further enhance magnetic anisotropy to further decrease switching current. The surface layer is Ta, Ti or Hf.

Abstract: A sensor device may include a substrate, and first and second semiconductor structures arranged over the substrate. The first semiconductor structure may be an ion-sensitive field effect transistor and may include a floating gate, and a sensing element electrically coupled to the floating gate. The second semiconductor structure may be capacitively coupled to the first semiconductor structure, and may include a first diffusion region and a second diffusion region having opposite polarity type dopants, and a channel region arranged therebetween. The second semiconductor structure may be configured to receive a bias voltage to tune an electrical characteristic of the first semiconductor structure through the first diffusion region and the second diffusion region and the channel region. In some embodiments, the substrate may be a crystalline-on-insulator substrate which may be coupled to a back gate bias to reduce an effective total capacitance of the ISFET and further improve the coupling ratio.

Abstract: A MEMS device including an active layer having a first surface and a second surface is provided. A first electrode and a second electrode, and at least one reconfigurable electrode segment are arranged over the first surface of the active layer. At least one reconfiguration layer is arranged over the second surface of the active layer. The at least one reconfigurable electrode segment and the at least one reconfiguration layer overlaps. One or more via contacts are disposed through the active layer configured to couple the at least one reconfigurable electrode segment and the at least one reconfiguration layer. The at least one reconfiguration layer is coupled to a reconfiguration switch for reconfiguring electrical connections to the at least one reconfigurable electrode segment. The MEMS device is configured to generate different resonant frequencies by reconfiguring the electrical connections to the at least one reconfigurable electrode segment using the reconfiguration switch.