Abstract: A resistive memory device is provided. The resistive memory device comprises a first electrode and a resistive layer over the first electrode, the resistive layer having a sidewall. A second electrode is over the resistive layer. An insulating liner is formed on the sidewall of the resistive layer. The insulating liner comprises two layers of different dielectric materials.

Abstract: A nonvolatile memory device is provided. The device comprises a floating gate having a first finger and a second finger and an active region below the floating gate fingers. A first doped region is in the active region laterally displaced from the first floating gate finger on a first side. A second doped region is in the active region laterally displaced from the first floating gate finger on a second side. A third doped region is in the active region laterally displaced from the second floating gate finger and the second doped region.

Abstract: A memory device may include a first conductor and a second conductor; a switching layer arranged between the first conductor and the second conductor, and one or more magnetic layers. The switching layer may be configured to have a switchable resistance in response to a change in voltage between the first conductor and the second conductor. The one or more magnetic layers may be arranged such that the one or more magnetic layers provide a magnetic field through the switching layer.

Abstract: Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming a structure for a laterally-diffused metal-oxide-semiconductor device. First and second source/drain regions are formed in a substrate, a gate electrode is formed over the substrate, an interconnect structure over the substrate, and a doped region is arranged in the substrate beneath the first source/drain region. The gate electrode is laterally positioned between the first and second source/drain regions, and the interconnect structure includes a contact connected to the first source/drain region. The doped region has a side edge that is laterally spaced from the contact by a distance.

Abstract: Structures including non-volatile memory elements and methods of fabricating a structure including non-volatile memory elements. First, second, and third non-volatile memory elements each include a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode. A first bit line is coupled to the first electrode of the first non-volatile memory element and to the first electrode of the second non-volatile memory element. A second bit line is coupled to the first electrode of the third non-volatile memory element.

Abstract: An inductive device may be provided, including a substrate and an inductive structure arranged over the substrate. The inductive structure may include a bottom metal winding layer; a top metal winding layer arranged further away from the substrate than the bottom metal winding layer; a magnetic core layer arranged between the bottom metal winding layer and the top metal winding layer; a connector arranged to electrically connect the bottom metal winding layer and the top metal winding layer; and a top metal ring element arranged around the top metal winding layer, spaced apart from the top metal winding layer. The inductive device may further include a guard ring element arranged under the top metal ring element and around the magnetic core layer, spaced apart from the magnetic core layer; wherein the guard ring element may include a magnetic material.

Abstract: A capacitor is provided. The capacitor includes a first conductive layer in a first isolation region in a substrate and a plurality of dielectric layers over the first isolation region. The plurality of dielectric layers may include inter layer dielectric (ILD) and inter metal dielectric (IMD) layers. The first conductive layer is a bottom plate of the capacitor. A second conductive layer is arranged over the plurality of dielectric layers, whereby the second conductive layer is a top plate of the capacitor and at least partially overlaps with the first conductive layer.

Abstract: According to various embodiments, a memory cell may include a substrate of a first conductivity type, the substrate having first and second regions of a second conductivity type spaced apart and defining a channel region therebetween. The memory cell may further include a word line arranged over a portion of the channel region nearer to the first region, an erase gate arranged over the second region, a floating gate arranged over another portion of the channel region nearer to the second region and between the word line and the erase gate, and a coupling gate arranged over a top end of the floating gate. The floating gate includes the top end, a bottom end, a first side extending from the top end to the bottom end and facing the erase gate, and a second side extending from the top end to the bottom end and facing the word line.

Abstract: The present disclosure generally relates to semiconductor devices, and more particularly, to semiconductor devices having memory cells for multi-bit programming and methods of forming the same. The present disclosure also relates to a method of forming such semiconductor devices. The disclosed semiconductor devices may achieve a smaller cell size as compared to conventional devices, and therefore increases the packing density of the disclosed devices.

Abstract: A nonvolatile memory device may be provided. The nonvolatile memory device comprises an active region, an n-well region and an isolation region separating the active region and the n-well region. A floating gate may be provided. The floating gate may be arranged over a portion of the active region and over a first portion of the n-well region. A first doped region in the active region may be laterally displaced from the floating gate on a first side and a second doped region in the active region may be laterally displaced from the floating gate on a second side opposite to the first side. A contact may be arranged over the n-well region, whereby the contact may be laterally displaced from a first corner of the floating gate over the first portion of the n-well region. A silicide exclusion layer may be arranged at least partially over the floating gate.

Abstract: A memory device may be provided, including first, second and third electrodes, first and second mask elements and a switching layer. The first mask element may be arranged over a portion of and laterally offset from the first electrode. The second electrode may be arranged over the first mask element. The second mask element may be arranged over the second electrode. The third electrode may be arranged over a portion of and laterally offset from the second mask element. The switching layer may be arranged between the first electrode and the third electrode, along a first side surface of the first mask element, a first side surface of the second electrode and a first side surface of the second mask element.

Abstract: A semiconductor device may be provided, including a first dielectric layer having a first region and a second region laterally adjacent to the first region. The semiconductor device may further include a bottom electrode at least partially arranged within the first region of the first dielectric layer, a memory element arranged over the bottom electrode, a top electrode arranged over the memory element, and a second dielectric layer arranged over at least the first region of the first dielectric layer. The second dielectric layer may surround the memory element and may surround at least a part of the top electrode. The semiconductor device may further include a third dielectric layer arranged over the second region of the first dielectric layer and laterally adjacent to the second dielectric layer, and a conductive interconnect arranged in the third dielectric layer and the second region of the first dielectric layer.

Abstract: A transistor device may be provided, including a substrate; a buffer layer arranged over the substrate; a source terminal, a drain terminal, and a gate terminal arranged over the buffer layer; a barrier layer arranged over the buffer layer; and a passivation layer arranged over the barrier layer. The gate terminal may be arranged laterally between the source terminal and the drain terminal, the barrier layer may include a recess laterally between the gate terminal and the drain terminal, a part of the gate terminal may be arranged over the passivation layer and the passivation layer may extend into the recess of the barrier layer.

Abstract: A semiconductor device is provided that includes a bond pad, an insulating layer, and a bonding structure. The bond pad is in a dielectric layer and the insulating layer is over the bond pad; the insulating layer having an opening over the bond pad formed therein. The bonding structure electrically couples the bond pad in the opening. The bonding structure has a height that at least extends to an upper surface of the insulating layer.

Abstract: A semiconductor device may be provided, including a substrate which includes a first semiconductor layer having a well region arranged within the first semiconductor layer, a buried insulator layer arranged over the first semiconductor layer, and a second semiconductor layer arranged over the buried insulator layer. The semiconductor device may include a capacitive structure including: the well region, at least one contact to the well region, at least a portion of the buried insulator layer over the well region, at least a portion of the second semiconductor layer, a source region and a drain region arranged over the second semiconductor layer, a gate dielectric layer arranged over the second semiconductor layer and arranged laterally between the source region and the drain region, and a gate layer arranged over the gate dielectric layer. The well region, the source region, and the drain region may have the same conductivity type.

Abstract: An illustrative device disclosed herein includes a first memory cell comprising a first memory gate positioned above an upper surface of a semiconductor substrate and a second memory cell comprising a second memory gate positioned above the upper surface of the semiconductor substrate. In this example, the device also includes a conductive select gate structure positioned above the upper surface of the semiconductor substrate between the first and second memory gates, wherein the conductive select gate structure is shared by the first and second memory cells.

Abstract: Structures for a split gate flash memory cell and methods of forming a structure for a split gate flash memory cell. A trench is formed in a semiconductor substrate. First and second source/drain regions are formed in the semiconductor substrate. A first gate is laterally positioned between the trench and the second source/drain region, and a second gate includes a portion inside the trench. The first source/drain region is located in the semiconductor substrate beneath the trench. A dielectric layer is positioned between the portion of the second gate inside the trench and the semiconductor substrate.

Abstract: According to various embodiments, an inspection device may include a chamber, a stage provided within the chamber, an electron emitter, a laser emitter, and a conductive probe. The stage may be configured to hold a sample. The electron emitter may be configured to emit an electron beam towards the stage, to generate a first electrical signal in the sample. The laser emitter may be configured to emit a laser beam towards the stage, to generate a second electrical signal in the sample. The conductive probe may be configured to receive from the conductive structure, at least one of the first electrical signal and the second electrical signal.

Abstract: Structures for a resistive memory element and methods of forming a structure for a resistive memory element. The resistive memory element includes a first switching layer, a second switching layer, a conductive spacer, a first electrode, and a second electrode. The first switching layer includes a portion positioned between the first electrode and the conductive spacer, the second switching layer includes a portion positioned between the second electrode and the conductive spacer, and the conductive spacer is positioned between the portion of the first switching layer and the portion of the second switching layer.

Abstract: A silicon controlled rectifier is provided. The silicon controlled rectifier comprises a substrate and a first n-well in the substrate. A p+ anode region may be arranged in the first n-well in the substrate. A first p-well may be arranged in the first n-well in the substrate. An n+ cathode region may be arranged in the first p-well in the substrate. A field oxide layer may be arranged over a first portion of the first p-well. A first gate electrode layer may extend over a second portion of the first p-well and over a portion of the field oxide layer.