Patents Assigned to GlobalFoundries U.S. 2 LLC
  • Patent number: 9318336
    Abstract: A high dielectric constant (high-k) gate dielectric for a field effect transistor (FET) and a high-k tunnel dielectric for a non-volatile random access memory (NVRAM) device are simultaneously formed on a semiconductor substrate. A stack of at least one conductive material layer, a control gate dielectric layer, and a disposable material layer is subsequently deposited and lithographically patterned. A planarization dielectric layer is deposited and patterned, and disposable material portions are removed. A remaining portion of the control gate dielectric layer is preserved in the NVRAM device region, but is removed in the FET region. A conductive material is deposited in gate cavities to provide a control gate for the NVRAM device and a gate portion for the FET. Alternately, the control gate dielectric layer may replaced with a high-k control gate dielectric in the NVRAM device region.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: April 19, 2016
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Nicolas Breil, Michael P. Chudzik, Rishikesh Krishnan, Siddarth A. Krishnan, Unoh Kwon
  • Patent number: 9269787
    Abstract: According to a bipolar transistor structure having a transistor top and a transistor bottom herein, a silicon substrate located at the transistor bottom has a collector region of a first conductivity type. An epitaxial base layer of a second conductivity type overlies, relative to the transistor top and bottom, a portion of the collector region. The epitaxial base layer has a bottom surface on the silicon substrate and a top surface opposite the bottom surface. A top region, relative to the transistor top and bottom, of the epitaxial base layer comprises a concentration of germanium having atomic compositions sufficient to avoid impacting transistor parameters, and sufficient to be resistant to selective chemical etching. A silicon emitter layer of the first conductivity type overlies, relative to the transistor top and bottom, a portion of the epitaxial base layer adjacent to the top surface of the epitaxial base layer.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: February 23, 2016
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: James S. Dunn, Qizhi Liu, James S. Nakos
  • Patent number: 9225715
    Abstract: A mechanism is provided for securely associating an application with a well-known entity. A determination is made as to whether an identified application has an associated certificate. Responsive to the identified application having the associated certificate, a determination is made as to whether the associated certificate is issued from a certificate authority associated with the well-known entity trusted by a user of the identified application, where the certificate authority is in a separate domain from an application marketplace where the application was obtained. Responsive to the associated certificate being issued by the certificate authority associated with the well-known entity trusted by the user of the identified application, an indication is provided to the user that the application is trusted in context to interactions with the certificate authority.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: December 29, 2015
    Assignee: GlobalFoundries U.S. 2 LLC
    Inventors: Patrick J. Bohrer, Colin K. Dixon, Jan S. Rellermeyer
  • Patent number: 9218488
    Abstract: A mechanism is provided for detecting malicious activity in a functional unit. For a current activity value associated with a functional unit, a determination is made as to whether a thermal level associated with the functional unit differs from a verified thermal level beyond a first predetermined threshold. Responsive to the thermal level associated with the functional unit differing from the verified thermal level beyond the first predetermined threshold, a determination is made as to whether there is a known profile of thread activity levels that substantially matches current thread activity levels. Responsive to identifying the known profile that substantially matches the current thread activity levels, thread activity levels are compared to the known profile of thread activity levels. Responsive to the thread activity levels differing from the known profile beyond a second predetermined threshold, an indication of suspected abnormal activity associated with the given functional unit is sent.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: December 22, 2015
  • Patent number: 9212914
    Abstract: Methods, systems, and articles of manufacture for event-based location sampling for map-matching are provided herein. A method includes determining a location of an object via a device associated with the object; determining one or more temporal sampling periods of one or more location information sensors at one or more sampling regions based on (i) said location of the object and (ii) one or more items of map-matching information; capturing one or more motion-related events associated with the object via the one or more location information sensors during the determined one or more temporal periods; and generating a trajectory of the object based on the one or more captured motion-related events.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: December 15, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Vinay K. Kolar, Ravindranath Kokku, Venkatadheeraj Pichapati
  • Patent number: 9207106
    Abstract: Systems and methods for incident detection are provided. A system for incident detection includes a network including at least one detector for detecting events in the network, a detection module capable of processing data from the at least one detector, and a calibration module capable of calibrating a plurality of bands for the incident detection based on a plurality of decision variables, wherein the plurality of bands define thresholds that are time-varying for all measurement locations in the network, and the thresholds are estimated using nonparametric quantile regression.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: December 8, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Laura Wynter, Ioannis Kamarianakis
  • Patent number: 9207105
    Abstract: Systems and methods for incident detection are provided. A system for incident detection includes a network including at least one detector for detecting events in the network, a detection module capable of processing data from the at least one detector, and a calibration module capable of calibrating a plurality of bands for the incident detection based on a plurality of decision variables, wherein the plurality of bands define thresholds that are time-varying for all measurement locations in the network, and the thresholds are estimated using nonparametric quantile regression.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: December 8, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Laura Wynter, Ioannis Kamarianakis
  • Patent number: 9202863
    Abstract: A structure is provided with a self-aligned resist layer on a surface of metal interconnects for use in forming air gaps in an insulator material and method of fabricating the same. The non-lithographic method includes applying a resist on a structure which has at least one metal interconnect formed in an insulator material. The method further includes blanket-exposing the resist to energy and developing the resist to expose surfaces of the insulator material while protecting the metal interconnects. The method further includes forming air gaps in the insulator material by an etching process, while the metal interconnects remain protected by the resist.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: December 1, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Daniel C. Edelstein, Elbert E. Huang, Robert D. Miller
  • Patent number: 9190479
    Abstract: An electrical contact structure distributes current along a length thereof. The electrical contact structure includes a plurality of n metal rectangles on n levels of metal. The rectangle on one metal level is at least as wide in width and vertically covers in width the rectangle on the metal level immediately below. The rectangle on one metal level is shorter in length than and substantially aligned at a first end with the rectangle on the metal level immediately below. Rectangle first ends are substantially aligned. Features of an exemplary FET transistor of this invention are a source and drain terminal electrical contact structure, a multi-level metal ring connecting gate rectangles on both ends, and a wider-than-minimum gate-to-gate spacing. The invention is useful, for example, in an electromigration-compliant, high performance transistor.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: November 17, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: David R. Greenberg, Jean-Olivier Plouchart, Alberto Valdes-Garcia
  • Patent number: 9190118
    Abstract: Multi-dimensional memory architectures are provided having access wiring structures that enable different access patterns in multiple dimensions. Furthermore, three-dimensional multiprocessor systems are provided having multi-dimensional cache memory architectures with access wiring structures that enable different access patterns in multiple dimensions.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: November 17, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Alper Buyuktosunoglu, Philip G. Emma, Allan M. Hartstein, Michael B. Healy, Krishnan K. Kailas
  • Patent number: 9190418
    Abstract: After forming source/drain trenches within a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate, portions of the trenches adjacent channel regions of a semiconductor structure are covered either by sacrificial spacers formed on sidewalls of the trenches or by photoresist layer portions. The sacrificial spacers or photoresist layer portions shield portions of the top semiconductor layer underneath the trenches from subsequent ion implantation for forming junction butting. The ion implantation regions thus are confined only in un-shielded, sublayered portions of the top semiconductor layer that are away from the channel regions of the semiconductor structure. The width of the ion implantation regions are controlled such that the implanted dopants do not diffuse into the channel regions during subsequent thermal cycles so as to suppress the short channel effects.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: November 17, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Anthony I. Chou, Murshed M. Chowdhury, Arvind Kumar, Robert R. Robison
  • Patent number: 9190471
    Abstract: A semiconductor structure including a semiconductor wafer. The semiconductor wafer includes a gate structure, a first trench in the semiconductor wafer adjacent to a first side of the gate structure and a second trench adjacent to a second side of the gate structure, the first and second trenches filled with a doped epitaxial silicon to form a source in the filled first trench and a drain in the filled second trench such that each of the source and drain are recessed and have an inverted facet. In a preferred exemplary embodiment, the epitaxial silicon is doped with boron.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: November 17, 2015
    Assignee: GLOBALFOUNDRIES U.S.2 LLC
    Inventors: Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Jinghong Li, Alexander Reznicek
  • Patent number: 9190313
    Abstract: Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: November 17, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Bruce B. Doris, Kangguo Cheng, Balasubramanian S. Haran, Ali Khakifirooz, Pranita Kerber, Arvind Kumar, Shom Ponoth
  • Patent number: 9190487
    Abstract: A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: November 17, 2015
    Assignees: GLOBALFOUNDRIES INC., GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Ali Khakifirooz, Thomas N. Adam, Kangguo Cheng, Shom Ponoth, Alexander Reznicek, Raghavasimhan Sreenivasan, Xiuyu Cai, Ruilong Xie
  • Patent number: 9190316
    Abstract: A stack that includes, from bottom to top, a nitrogen-containing dielectric layer, an interconnect level dielectric material layer, and a hard mask layer is formed on a substrate. The hard mask layer and the interconnect level dielectric material layer are patterned by an etch. Employing the patterned hard mask layer as an etch mask, the nitrogen-containing dielectric layer is patterned by a break-through anisotropic etch, which employs a fluorohydrocarbon-containing plasma to break through the nitrogen-containing dielectric layer. Fluorohydrocarbon gases used to generate the fluorohydrocarbon-containing plasma generate a carbon-rich polymer residue, which interact with the nitrogen-containing dielectric layer to form volatile compounds. Plasma energy can be decreased below 100 eV to reduce damage to physically exposed surfaces of the interconnect level dielectric material layer.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: November 17, 2015
    Assignees: GLOBALFOUNDRIES U.S. 2 LLC, ZEON CORPORATION
    Inventors: Markus Brink, Robert L. Bruce, Sebastian U. Engelmann, Nicholas C. M. Fuller, Hiroyuki Miyazoe, Masahiro Nakamura
  • Patent number: 9184948
    Abstract: A Decision Feedback Equalizer (‘DFE’) that includes: a plurality of input signal lines comprising at least one data signal line and a plurality of power control signal lines; at least one output signal line; and a plurality of independently-controlled isolated power domains, where each independently-controlled isolated power domain is coupled to a corresponding one of the power control signal lines, each of the power control signal lines configured to transmit a power control signal to the independently-controlled isolated power domain dynamically, and each independently-controlled isolated power domain selectively consumes power in response to the power control signal, each independently-controlled isolated power domain configured to be dynamically powered up or powered down without impacting signal processing operations.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: November 10, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Minhan Chen, Steven M. Clements, Carrie E. Cox, Todd M. Rasmus
  • Patent number: 9183367
    Abstract: Voice based biometric authentication method, apparatus (system), and computer program product. Provided is voice verification solution with a high accuracy rate that can prevent cheating via recording. The method includes: transmitting to the user a question prompt requiring the user to speak out a voice segment and an answer to a dynamic question, the voice segment having a corresponding text dependent speaker verification model enrolled before the authentication; segmenting, in response to receiving the voice answer, the voice segment part and the dynamic question answer part out from the voice answer; and verifying boundary smoothness between the voice segment and the answer to the dynamic question within the voice answer. With this method, whether a voice answer relates to cheating via recording is determined according to the degree of smoothness at a detected boundary. The apparatus and computer program product carry out the steps of the above-mentioned method.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: November 10, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Sheng Hu Bao, Min Li, Yong Qin, Zhong Su, Liu Wen, Shi Lei Zhang
  • Patent number: 9183286
    Abstract: A method for analyzing predefined subject matter in a patent database being for use with a set of target patents, each target patent related to the predefined subject matter, the method comprising: creating a feature space based on frequently occurring terms found in the set of target patents; creating a partition taxonomy based on a clustered configuration of the feature space; editing the partition taxonomy using domain expertise to produce an edited partition taxonomy; creating a classification taxonomy based on structured features present in the edited partition taxonomy; creating a contingency table by comparing the edited partition taxonomy and the classification taxonomy to provide entries in the contingency table; and identifying all significant relationships in the contingency table to help determine the presence of any white space.
    Type: Grant
    Filed: June 3, 2008
    Date of Patent: November 10, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Ying Chen, Jeffrey Thomas Kreulen, James J. Rhodes, William Scott Spangler
  • Patent number: 9184129
    Abstract: The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a heating element for directly heating the antifuse dielectric layer during programming.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: November 10, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Byeongju Park, Subramanian S. Iyer, Chandrasekharan Kothandaraman
  • Patent number: 9182686
    Abstract: Spacers arranged on opposite sides of an article to be processed into an EUV pellicle support the article. Plates on opposite ends of the spacer-article combination include respective electrodes. The plates, article, and spacers can be held together with a vacuum retention system. A center hole of each spacer forms a chamber with surfaces engaged by the spacer. A fluid entry extending from an outer surface of each spacer to its center hole allows delivery of fluid to each chamber. Additional spacers can be used to support additional articles. Additional plates and electrodes can also be used.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: November 10, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventor: Dario L. Goldfarb