Abstract: An improvement to system clock synchronization corrector in a digital transceiver allows the generation of a phase error correction signal for use in an imbedded clock synchronization control loop without the use of additional transmitted information or additional external circuitry. The system allows a transceiver to achieve timing and synchronization lock to a system master clock, such as a T1 or E1 clock, by triggering a counter to supply a count responsive to a higher-frequency replica of the local clock signal with the network clock signal. A network timing reference unit generates a phase error offset by clocking data into comparison registers in response to the maximum counter values. Subsequent counter values are mathematically combined to generate a series of phase offset samples. The phase error samples may be stored and or further manipulated to generate a phase error correction signal for use in a clock synchronization control loop.

Abstract: An improved line driver-hybrid and method for increasing the power efficiency, signal accuracy, and stability of a transmit signal on a transmission line are disclosed. The improved line driver-hybrid uses a negative feedback control loop, thereby enhancing operational stability and suppressing both amplifier imperfections and discrete component manufacturing variances. Furthermore, the improved line driver-hybrid provides a power efficient full duplex solution for line driver applications. The present invention can also be viewed as providing a method for actively terminating a transmission line.

Abstract: An embodiment of the present invention is related to an analog-to-digital converter comprising a polyphase combiner comprising at least a first combiner filter and a second combiner filter for receiving a plurality of inputs and generating a combined signal. The analog-to-digital converter also comprises a multistage decimator structure for receiving the combined signal and generating a digital sigma-delta output, the multistage decimator structure comprising at least a first decimator comprising a first integrator filter; a first downsampling block and a first differentiator; and a second decimator comprising a second integrator filter; a second downsampling block and a second differentiator.

Abstract: A system and method for modifying the spectrum allocation for DSL and LAN signals in accordance with bandwidth requirements of a small office, home office (SOHO) network is disclosed. After initiation of computers within the SOHO network, a handshake procedure is performed between the SOHO network and a wide area network (WAN). The handshake procedure discloses bandwidth requirements for the SOHO network to perform local communication between local area networks (LANs), and for the SOHO network to communicate with the WAN. As a result, the system modifies the spectrum allocation for digital subscriber line (DSL) and LAN signals associated with the SOHO network such that maximum bandwidth allocation is provided in accordance with actual bandwidth need.

Abstract: A multi-channel communication link generates a transport data protocol unit (TPDU) corresponding to each data packet received at a particular interface in a packet switching network. Each TPDU may comprise a data packet in accordance with a standard data transfer protocol and a modified header comprising a sequence number responsive to the relative position of the data packet within a data stream. The multi-channel communication link may inverse multiplex the various TPDUs for transmission across a plurality of asynchronous communication lines. A multi-channel communication link in accordance with the present disclosure may comprise a source first-in first-out (FIFO) buffer, a source line multiplexer/demultiplexer, a plurality of asynchronous communication links, a destination line multiplexer/demultiplexer, and a destination FIFO buffer. The present disclosure also provides a method for transferring data between computing devices via a virtual transport link.

Abstract: A system and a method for constructing a signal integrity supervisor capable of both detecting and triggering an appropriate response when transmit path signals indicate a potential damaging transmitter operating mode. The system and method of the present invention takes advantage of the inherent property of a Delta-Sigma Modulator (DSM) which makes the probability of encountering a long string of consecutive ones or zeroes during nominal operation very small. The signal integrity supervisor ensures safe transmitter operation by monitoring the data and the clock inputs to a digital to analog converter. The system may comprise a data signal supervisor and a clock signal supervisor. The data supervisor may comprise a comparator and a counter and may be configured to power down a line driver upon detecting a data stream having a continuous voltage level.

Abstract: The present invention is directed to a signal processing and amplifying system that uses advance knowledge of a digital signal, before it is converted to analog form and applied to the input stage of the amplifier stage, to “intelligently” amplify the signal with the maximum power efficiency and minimal distortion. This advance knowledge of the digital signal allows a switch control logic (SCL) unit to open and close solid state switches and seamlessly turn off and on the low and high power stages correctly to minimize the amplifier distortion while conserving power. In one embodiment, the system comprises a shift register, which receives the supplied digital signal to be amplified and delays the digital signal by a known amount, a digital to analog converter, an amplifying circuit, which is made up of at least two amplifiers, and an SCL unit. The SCL unit comprises control logic, and multiple solid state switches.

Abstract: The present invention is directed to a system and method for determining when a particular tone in a discrete multi-tone communications system is being used to transmit a control signal. Broadly, the system and method of the present invention are realized by a digital signal processor that is configured to detect a constant phase shift on individual tones when a control signal condition is present.

Abstract: An improved line driver and method for increasing the available signal transmit power on a transmission line are disclosed. The improved line driver achieves an available transmit power increase without increasing the maximum current in the line driver output stage. The output stage of the line driver may comprise a first amplifier, a second amplifier, and an integrated back-matching resistor network. In order to further increase the available transmit power; a protective semiconductor device may be added to a line driver output stage for each semiconductor device in the first and second amplifiers. A third embodiment of a line driver output stage in accordance with the present invention may comprise a combination of the integrated back-matching resistor network along with the protective semiconductor devices.

Abstract: In accordance with one aspect of the invention, an apparatus is provided having a transmit path and a receive path for communicating data. The apparatus includes an analog to digital (A/D) converter that is disposed in communication with the receive path. The A/D converter operates at a first sampling rate, and it converts a received analog signal into a digital signal. The apparatus also includes a first echo canceller that is in communication with the receive path and that operates at the first sampling rate for estimating a first portion of an echo signal leaking from the transmit path to the receive path. The estimated echo signal is subtracted from the digital signal. The amplitude of the digital signal is increased by a digital gain. A decimator is disposed in communication with the receive path, whereby the decimator filters the digital signal that has a first sampling rate and emits a signal output at a reduced sampling rate.

Abstract: Devices and method for effectively filtering a signal, particularly for a communication system, are disclosed. In this regard, an exemplary embodiment of the present invention may be construed as an AFE that includes a high-pass receive filter for a communication system. The filter includes an AC-coupled capacitive input and a plurality of RC integrators. At least one of the plurality of RC integrators includes a damping resistor in parallel with a feedback capacitor and a switch for enabling the damping resistor, such that when the damping resistor is enabled, the at least one RC integrator is damped so as to reduce DC instability.

Abstract: A system and method to perform partial byte writes in a processor circuit is disclosed. The system comprises a bit assembly circuit having a bit assembly register with a corresponding shadow register. Also included is a bit routing circuit configured to transfer at least one data bit from a data bus to a predetermined register position in the bit assembly register and a shadow bit from the data bus to a corresponding register position in the shadow register. The shadow bit indicates that the data bit written comprises valid data. The bit assembly and shadow registers may receive data directly from the data bus as well. Using this circuitry, a partial parallel data block is assembled in the bit assembly register. Thereafter, the partial parallel data block is transferred to a destination register via the data bus with corresponding shadow bits being transmitted to the destination shadow register. The valid data is processed accordingly.

Abstract: A system, method, and apparatus are disclosed for minimizing the memory required by memory management structures in a multi-threaded operating environment. The shortest necessary lifetime of a memory management structure is determined to allow the memory required to maintain the memory management structure to be reallocated for other uses when the memory management structure is no longer required. A memory management structure comprises a synchronization object for each data segment. A link list of synchronization nodes is also maintained to identify to the read thread a next data segment to be read and comprises a segment ready indicator that also indicates whether a data segment is available for access. If the segment ready indicator indicates to the read thread that the data segment is available for access, the read thread proceeds directly to reading the data segment without accessing the synchronization object.

Abstract: An RF device including a control loop for maximizing output power for each of several data rates or constellation types. The RF device includes a power detector, a power amplifier and a MAC that includes input and output adjust circuits. A power level value is generated from measured output power. The MAC compares an adjusted power level value with a set point value and generates an error value. The MAC adjusts a power control value based on the error value for controlling the gain of the power amplifier. The MAC uses a data rate signal indicative of a selected constellation type or data rate. The input adjust circuit stores one or more input adjustment values selected by the data select signal for adjusting the power level value. The output adjust circuit stores one or more output adjustment values selected by the data select signal for adjusting the power control value.

Abstract: The present invention is directed to a system and method for upgrading a telecommunication system including a central office (CO), a digital loop carrier (DLC), and a plurality of customer premises equipment (CPE). Broadly, the present invention is realized by the retrofit of a DLC to enable the DLC to communicate with a CO through high bandwidth wireless transmissions. The high bandwidth wireless transmissions accommodate much larger data throughput than previously accommodated through the copper “backhaul” of multiple T1 circuits. In accordance with one aspect of the present invention, a telecommunications system comprises a CO, a DLC, and a plurality of CPE. Each of the plurality of CPE are electrically connected to the DLC. A radio frequency (RF) interface circuit is disposed at the DLC, along with one or more DSL line cards. A first wireless transceiver disposed at the DLC, and is electrically connected to the radio frequency interface circuit.

Abstract: A data bus address extender is presented. The data bus extender may be deployed in cooperation with a master device to extend the number of addressable physical devices on a data bus without modifying the number of address bits used to identify the various slave devices on the bus. The data bus extender of the present invention can be used in existing data bus systems with minimal impact as it does not require a change at the slave devices. A data bus address extender in accordance with the present invention may comprise an address stripper and a range select decoder wherein at least one of the address bits at the slave side of the bus is enabled by the range select decoder. The present invention also provides a method for extending the number of addressable communication devices on a data bus.

Abstract: The present invention is directed to a system and method that detects periods of no activity in the downstream data path of a DSL modem and reduces the transmit power in the output line driver to reduce power consumption in the modem. A preferred method is operative at the central office DSL modem and comprises detecting periods of no activity in the downstream data bins, reducing the transmit power in response to the inactivity on the communication link, detecting either upstream or downstream data, and performing a fast retrain of the modem to restore nominal power data transmission in the downstream direction. A variation of the preferred method uses a reduced point constellation encoding scheme to reduce power consumption. Broadly, the system of the present invention may be realized by a configurable transmit channel line driver and a digital signal processor.

Abstract: A method and apparatus for encoding data bits in DMT modulation system is providing utilizing a 64-state Trellis encoder to achieve further improvement in the achievable coding gain by employing coset partitioning, bit conversion, and constellation encoder that fit the DMT modulation. The coding gain of the new coder is around 5.63 dB, which is about 0.96 dB higher than the current Trellis coder in the DMT standard.

Abstract: The present invention relates to improved ADC buffers and AFEs for high frequency applications, such as VDSL. The present invention can also be programmably configured for other xDSL applications. In this regard, a buffer circuit for a high-bandwidth analog-to-digital converter (ADC) includes a first unity-gain buffer configured to receive an analog input signal. The first unity-gain buffer includes a MOSFET differential amplifier with a current mirror load and a transient-reduction network electrically interconnected with the MOSFET differential amplifier and configured to reduce transient energy emitted by the ADC. The buffer circuit also includes a second unity-gain buffer cascaded to the first unity-gain buffer and configured to provide the analog input signal from the first unity-gain buffer to the ADC.

Abstract: The present invention is directed to a system and method for establishing a point to multipoint communication network. Preferable, the point to multipoint communication network is established in the environment of a home of small office, and the invention is realized through a computer that may dynamically establish both LAN and WAN communications. Broadly, the system and method of the present invention are realized by a computer that is configured to assume a role as either a Master or a Slave on a LAN. If the computer is the first (or only) computer powered up on the LAN, then it assumes the role of Master. In this role, the computer establishes a communication link with a WAN (such as with an Internet Service Provider), and directs all WAN communications over the WAN, using a WAN frequency and protocol (such as DSL). As other computers join the LAN, then WAN communications from those computers are relayed through the Master to the WAN.