Abstract: An adaptive filter for echo cancellation includes a segmented sparse transversal filter having an input, the filter having an adjustable length, adjustable lengths for the segments and adjustable tap weights. The adaptive filter further includes an adaptive tap weight control mechanism providing a tap weight vector including tap weights and a tap weight vector length to the taps of the transversal filter, the adaptive tap weight control mechanism setting the tap weights and the tap weight vector length in response to comparison of estimated truncation error to a target truncation value and in response to a magnitude of integrated cross correlation coefficients between a reference signal and an error signal from the adaptive filter.

Abstract: The present invention is directed to a computer system having novel circuitry for coupling peripheral cards to a power line network. In this regard, the computer includes a switching power supply having coupling circuitry for coupling an electrical signal with a power line, a filter circuit electrically connected to the coupling means for receiving an electrical signal from the coupling means and filtering the received signal, and an amplifier circuit electrically connected to the filter circuit for amplifying the filtered signal. The computer system also includes at least one peripheral circuit (e.g., PC card). An infrared transmitter is coupled to the amplifier circuit for transmitting an infrared signal. Finally, the computer includes an infrared receiver coupled to the peripheral circuit for receiving the scattered infrared signal. In accordance with another embodiment of the invention, a power line adapter is provided for communicating signals between a power line and a computer.

Abstract: The present invention is directed to an apparatus and system for selectively inhibiting access to a memory during a DMA block transfer. In accordance with one embodiment of the present invention, the system includes memory, a DMA engine, and logic configured so that when a control signal is asserted, the logic blocks the DMA engine's request for access to memory and generates an acknowledgment of the request, such that the DMA engine performs a DMA transfer without accessing data in memory.

Abstract: A system and method for ADSL USB bandwidth negotiation are presented. The system comprises a modem that is configured to transfer data between an ADSL line and a USB bus and that is further configured to receive an ADSL line rate setting, submit an isochronous bandwidth request to a computer, reduce the isochronous bandwidth request in response to the availability of isochronous bandwidth, modify the ADSL line rate setting in response to the availability of isochronous bandwidth, and modify the USB bus transfer mode in response to the availability of isochronous bandwidth. The method comprises steps of receiving an ADSL line rate setting, submitting an isochronous bandwidth request to a computer, reducing the isochronous bandwidth request in response to the availability of isochronous bandwidth, modifying the ADSL line rate setting in response to the availability of isochronous bandwidth, and modifying the USB bus transfer mode of the ADSL USB modem in response to the availability of isochronous bandwidth.

Abstract: A system and method for determining fault path behavior in a computer software system. An error or event, the occurrence of which is to be tested, is assigned a probability value and an array of elements populated by pseudo-random numbers. Upon each operation of the system under test the current array value is compared against the probability value. If the current array value is greater than or equal than the probability value, the error or event is simulated within the software. Otherwise, the event is not simulated and the software is left to operate conventionally. The array is incremented upon each occurrence of the system under test.

Abstract: Methods and systems for tuning an RC continuous-time filter are disclosed. In this regard a representative system for tuning an RC continuous-time filter includes a coarse-tuned resistive element coupled to an input of the filter for varying the cut-off frequency of the filter based upon process variations. The system also includes a MOSFET transistor coupled to the resistive element. The MOSFET transistor provides a resistance dependent upon a voltage offset provided to the gate of the transistor, wherein the resistance of the transistor offsets an adjustment in the resistance of the resistive element caused by temperature variations. The system also includes a voltage offset generator configured to provide the voltage offset to the transistor.

Abstract: Methods and systems for processing data are disclosed. An exemplary system for parsing and modifying data stored in an array of storage elements includes a parsing system configured to access the data stored in selected storage elements of the array of storage elements and output the data in one of a plurality of register formats and a write system configured to write data to selected storage elements of the array of storage elements, wherein the data is received in one of the plurality of register formats. The plurality of register formats includes a first set of register formats corresponding to a packed representation of the data and a second set of register formats corresponding to an unpacked representation of the data.

Abstract: The present invention is directed to a system and method for minimizing signal distortion in a discrete multi-tone communications system that is being used in both the POTS and the ADSL frequency bands. Broadly, the system and method of the present invention are realized by a digital signal processor that is configured to insert a probe signal into the upstream channels of the communication system, measure the resulting signal distortion in the downstream channels, and adjust the upstream signal power to minimize system signal distortion due to the upstream data transmission. The system and method further estimates the POTS band signal distortion based on the measured distortion at the higher frequencies, and adjusts the output signal power at the central office equipment to minimize signal distortion at the customer premises.

Abstract: The present invention is generally directed to a novel method of computing a fast Fourier transform (FFT), and an associated circuit that controls the addressing of a data memory of the FFT processing circuit. The novel method operates by computing all complex butterfly operations in a given stage of computations, before computing any of the complex butterfly operations in a subsequent stage. Further, and within any given computation stage, the method performs by computing all other complex butterfly operations in a given stage of computations having a twiddle factor equal to the first twiddle value of that stage, before computing any other complex butterfly operations in the given stage of computations. Thereafter, subsequent computations are performed in the same way.

Abstract: A combined cable/digital subscriber line (DSL) modem and method for data transmission. Upstream data is transmitted to a data communications network through a two wire pair to a central office using unidirectional DSL transmission. Downstream data is transmitted from the data communications network to the combined cable/DSL modem via a cable network using unidirectional cable transmission. Thus, bi-directional data communications is established using two unidirectional transmission links for faster and more efficient data communication.

Abstract: A system and method is presented for dividing a reference clock frequency by any real number. The invention allows for a real number divisor that could have any desired degree of precision. Additionally, the invention seeks to minimize hardware complexity in realizing such a reference-clock frequency divider. In one particular embodiment of the invention, a system and method is presented, wherein the real number divisor is a real number having a repeating decimal (i.e., the real number may be represented by a fraction).

Abstract: Systems and methods are provided for implementing: a rings architecture for communications and data handling systems; an enumeration process for automatically configuring the ring topology; automatic routing of messages through bridges; extending a ring topology to external devices; write-ahead functionality to promote efficiency; wait-till-reset operation resumption; in-vivo scan through rings topology; staggered clocking arrangement; and stray message detection and eradication. Other inventive elements conveyed include: an architectural overview of a packet processor; a programming model for a packet processor; an instruction pipeline for a packet processor; and use of a packet processor as a module on a rings-based architecture.

Abstract: A SINC filter for an oversampling Sigma-Delta digital to analog converter (OSDAC) having a cascaded construction that results in reduced sensitivity to capacitor mismatch. Specifically, the SINC filter circuit filter may be defined by a transfer function H(z), which is further defined by first constituent transfer functions H1(z) and H2(z). The constituent transfer functions may be implemented in a cascaded fashion. Preferably, one of the cascaded sections includes a resistor string that defines a plurality of reference voltages. A plurality of switching elements are configured to controllably switch these reference voltages to a capacitor of a tap.

Abstract: A processing circuit is disclosed for computing a fast Fourier transform (FFT). In one embodiment, the processing circuit includes a memory device, a multiplier, a detector, a state machine, and a circuit for performing the 2's compliment of a coefficient. The memory storage device stores data values and coefficient (or twiddle) values. The detector integrates a data pointer with the state machine. The detector is designed to identify the symmetry lines (by memory address). The state machine, when notified by the detector that a line of symmetry has been encountered, appropriately adjusts either the coefficients, the imaginary sign, or the real sign for input to a multiplier.

Abstract: In accordance with one aspect of the invention, an apparatus is provided for facilitating combined xDSL and POTS communication across a two wire pair. The apparatus includes a first communication port for communication with a central office across a two wire pair, and a second communication port for communication with a customer premises across a two wire pair. A splitter, or tap, is disposed at the first communication port for splitting a combined xDSL and POTS signal into a first and second signal path. A low pass filter is disposed in the first signal path for filtering the xDSL signal from the combined signal in the first signal path, leaving only the low-frequency (POTS frequency) signals. A circuit is disposed in the second signal path that is configured to filter the POTS signal from the combined signal, leaving only the xDSL signal.

Abstract: A one-wire protocol is described, wherein a one-wire bus has either a wired-AND configuration or a wired-OR configuration. In this protocol, data is encoded using time modulation. In one embodiment, two devices communicate with each other through the one-wire bus. One device is configured to transmit data by driving the one-wire bus high, while the other device is configured to transmit data by driving the one-wire bus low. In a preferred embodiment, transmission of data by each of the two devices is interleaved in such a fashion so that there is a bit-for-bit exchange between one device and the other device. In another embodiment, more than two devices may communicate through the one-wire bus.

Abstract: A system and method for performing peak-to-average power ratio reduction in a transmitter using pulse amplitude modulation (PAM) encoding. Broadly, a transmitter is configured to perform active digital filtering to detect encoded data symbols that if uncorrected would lead to relatively high analog signal peaks in the data transmission. A prediction is made of the peak values that would be applied at the digital to analog converter (DAC) if the original output of the Tomlinson precoder was sent into the shaping filter. If the absolute value of the predicted peak value exceeds a threshold, a correction of a full 2L step is applied for one sample of the Tomlinson precoded stream. The correction step is applied in such a way as to reduce the resulting peak output. Two methods of predicting the peak values are presented. The first method segments the shaping filter into causal and non causal portions so that no extra delay is introduced.

Abstract: A system and method for filter tuning are presented. The system comprises means for adjusting the components of a filter by coarse adjustments such that the filter is set with an initial cutoff frequency of adequate accuracy to satisfy the requirements of the filter application, and means for adjusting the components of the filter by fine adjustments such that the filter is set to maintain the accuracy of the initial cutoff frequency in response to cutoff frequency drift. The method comprises the steps of adjusting the components of a filter by coarse adjustments such that the filter is set with an initial cutoff frequency of adequate accuracy to satisfy the requirements of the filter application, and adjusting the components of the filter by fine adjustments such that the filter is set to maintain the accuracy of the initial cutoff frequency in response to cutoff frequency drift.

Abstract: A system and method for providing additional voltage to an amplifier circuit, wherein the voltage is supplied using a single voltage supply and the amplifier voltage rail is configured to track the amplitude of the input signal.

Abstract: The present invention is directed to a system and method that efficiently, accurately, and quickly detects a suitable stored fast retrain profile to permit the resumption of ADSL communications in the presence of changing line conditions in a dual POTS/ADSL communications system. The method of the present invention is based on measuring the amplitude and phase of a few discrete multi-tone tones in the receiver portion of a communications system and recording the number of times a profile is selected to replace a preceding profile. Broadly, the system and method of the present invention are realized by a digital signal processor that is configured to detect a fast retrain request, select a suitable stored profile, and apply the parameters associated with the selected profile to configure the customer premises modem.