Abstract: The present invention is directed to a system and method for reducing the need to perform signal clipping in a DMT transmitter. In accordance with one aspect of the invention, a method performs an inverse Fourier Transform on the input to produce a time-domain, digital value to be transmitted to a remote receiver. The method then evaluates the magnitude of the digital value to determine whether the magnitude exceeds a threshold value. Then, the method alters the input and re-performs an inverse Fourier Transform on the altered input, only if the step of evaluating the magnitude determines that the magnitude of the digital value exceeds the threshold value.

Abstract: A continuous-time smoothing filter circuit and method for implementing the same are disclosed. The circuit may be implemented as a cascade of two sections. The first section may comprise two programmable 3rd order low-pass filters, each filter having a low Q value complex pole pair, as well as, a negative real pole. The second section may comprise an output stage amplifier having a low output impedance in order to drive external loads. Each of the 3rd order low-pass filters may be under programmable control to select and coarsely tune the cut-off frequency for each of the two filters. In its broadest terms, the method of the present invention can be described as: processing a digital to analog converter generated output signal with a first 3rd order low-pass filter; processing a first output signal provided by the first 3rd order low-pass filter with a second 3rd order low-pass filter; and processing a second output signal provided by the second 3rd order low-pass filter with a low-output impedance amplifier.

Abstract: An ADSL system for operating in a time duplex system that provides alternative configurations for limiting crosstalk in a broadband network is disclosed. The ADSL system introduces a trial bitmap profile configuration to maximize the bit rate at which information is transmitted, regardless of network topology. In a simplified embodiment, a composite signal to noise ratio is derived from a minimum far end crosstalk signal to noise ratio and a minimum near end crosstalk signal to noise ratio. A maximum bit rate for the transfer of information, which is directly related to the derived composite SNR, is then determined. Information is then transmitted simultaneously between an asymmetric digital subscriber line central office and an asymmetric digital subscriber line customer premise at the determined maximum bit rate.

Abstract: In general, the line driver is defined by an input and output stage wherein the input stage is identified by the deriving of the open loop gain of a preamplifier and the output stage is defined by the deriving of the open loop gain of two drivers that provide power required for the line driver to drive a line. Both, the preamplifier and the drivers have inputs that sit at a common mode voltage, thereby inhibiting a common mode input voltage swing and limiting distortion in the line driver. The gain of the preamplifier may be changed to a desired value by regulating the values of resistors therein, thereby reducing distortion by maximizing the open loop gain for all lines and DSL applications. The line driver can be configured for any desired closed loop gain, regardless of whether the gain value is below or above 1. The drivers of the, output stage use a set of programmable output devices to allow for maximum drive capability of the drivers to be programmed under digital control.

Abstract: An improved method and apparatus for active line termination is disclosed. An active termination line driver (ATLD) includes a pair of power amplifiers configured to amplify a transmit signal, the amplifiers comprise a first input for receiving the transmit signal, a second input for receiving a feedback signal, and an output configured to provide the amplified transmit signal to the load. The ATLD also includes a resistive network configured to provide the feedback signal from the outputs of the amplifiers to the second inputs power amplifiers. The resistive network is selectively configured to facilitate any one of a plurality of feedback configurations to emulate a back-matching impedance. Other embodiments of the present invention may be construed as methods for power efficiently driving a transmit signal to a load.

Abstract: The present invention is generally directed to a processing circuit for computing a fast Fourier transform (FFT). The present invention reflects the recognition that excessive reads to and writes from memory consume excessive amounts of power. Accordingly, the circuit of the present is specifically designed to minimize the number of reads and writes to memory. In addition, the circuit is designed so that processing parallelism may be achieved in order to reduce the total number of clock cycles required to compute a FFT. In accordance with one aspect of the invention, the processing circuit includes a data memory for storing data values, and a separate coefficient memory for storing coefficient (or twiddle) values. The circuit further includes a multiplier configured to multiply values received from the coefficient memory and another value retrieved from some other location.

Abstract: An improved line driver and method for increasing the available signal transmit power on a transmission line are disclosed. The improved line driver achieves an available transmit power increase by limiting the output stage signal path to NMOS and NPN bipolar semiconductor devices. The output stage of the improved line driver may comprise a first amplifier, a second amplifier, a first transformer, a second transformer, and a plurality of back-matching resistor networks. A second embodiment of an improved output stage of a line driver may comprise a first amplifier, a second amplifier, a transformer, and a plurality of back-matching resistor networks. Both preferred embodiments may be implemented with CMOS and bipolar semiconductor devices, as well as, a combination of the two semiconductor technologies.

Abstract: A two-stage op-amp circuit including a double-cascode telescopic op-amp circuit in the input stage and a fully-differential op-amp circuit in the output stage and having very high open-loop DC gain, very high unity-gain frequency, and relatively very low power consumption is presented. The input stage op-amp circuit and the output stage op-amp circuit are each comprised of a plurality of electrically connected MOSFET's. The input stage op-amp circuit provides very high gain, high input resistance, and large common mode rejection. The output stage op-amp circuit provides gain, low output resistance, and minimal output loss.

Abstract: A circuit and method that provides a one-step real time pointer for interleaving/deinterleaving that uses a single modulo operation is disclosed. The single modulo pointer of the present invention may be used to increase data throughput through a data interleaver/deinterleaver. A memory address pointer consistent with the present invention may be implemented with a multiplexer, an adder, a counter, and a modulo operator. A method for convolutional interleaving/deinterleaving is also disclosed.

Abstract: A system and method for characterizing a transmission line in a digital subscriber line (DSL) system. Broadly, the method uses DSL system components, which are configured to perform time domain reflectometry (TDR), in order to determine transmission line characteristics.

Abstract: A physical interface unit and method are disclosed which are configured to receive a data stream which may use any one of a number of data communications protocols, and to transmit the same data stream using another one of the same number of data communications protocols. The physical interface unit is advantageously designed to operate in conjunction with a processor circuit to translate a data stream from a first data protocol to a second data protocol. The physical interface unit includes a first serial interface, a first asynchronous transfer mode (ATM) interface, and a first parallel interface. The physical interface also includes a second serial interface, a second ATM interface, and a second parallel interface. The first serial, ATM, and parallel interfaces are electrically coupled to a first FIFO circuit which interfaces with the processor circuit. Likewise, the second serial, ATM, and parallel interfaces are electrically coupled to a second FIFO circuit which interfaces with the processor circuit.

Abstract: A line driver is disclosed. Generally, the structure of the line driver contains an amplifier stage that can operate at various voltage levels. The first external supply voltage is connected to a first power supply input of the amplifier stage. The line driver also includes a charge pump that generates at least a first internal supply voltage supplied to the amplifier stage. A switch control circuit is also included within the line driver to regulate the voltage output from the charge pump. Systems and methods for supplying various voltages to a load are also disclosed.

Abstract: In general, a system and method for implementing DSL support for use by a computer having a PCI bus is disclosed. A DSL modem is allowed to simultaneously communicate data to and from the computer. In a simplified embodiment, a DSL enabling device provides both data flow control and general control functions of the DSL modem. The DSL enabling device comprises a PCI DMA arbitrator, which determines the status of a temporary memory module in response to either a transmit request from a transmit control unit or a receive request from a receive control unit, thereby arbitrating between the two control units in order to access the temporary memory module. A read/write register specifies priority between the transmit control unit and the receive control unit, as well as specifying computer memory addresses to write to and setting memory cell length.

Abstract: The present invention is generally directed to a novel method of computing a fast Fourier transform (FFT), and an associated circuit that controls the addressing of a data memory of the FFT processing circuit. The novel method operates by computing all complex butterfly operations in a given stage of computations, before computing any of the complex butterfly operations in a subsequent stage. Further, and within any given computation stage, the method performs by computing all other complex butterfly operations in a given stage of computations having a twiddle factor equal to the first twiddle value of that stage, before computing any other complex butterfly operations in the given stage of computations. Thereafter, subsequent computations are performed in the same way.

Abstract: A resource optimized interleaving/deinterleaving system comprising a Reed-Solomon encoder, a Reed-Solomon decoder, a state machine, and a memory is disclosed. Reed-Solomon encoded fastpath data is stored in memory. A stream of interleaved data with predefined parameters S, the number of DMT symbols per each Reed-Solomon codeword, D, the interleaving depth, and N, the block length is written into system memory at an adaptable rate determined by the Reed-Solomon encoder. The previously stored Reed-Solomon encoded fastpath data is automatically reassembled and buffered with the interleaved data to form appropriate DMT transmission symbols. The DMT transmission symbols are then read out of the system memory at a rate determined by the next processing function, i.e., tone ordering. A method of using one Reed-Solomon encoder/decoder with the integrated interleaving/deinterleaving system to support dual single latency DMT systems is also disclosed.

Abstract: In general, a system and method for providing PCI power management support without requiring a clock is disclosed. A computer is allowed to reside in a sleep mode and receive a power management event signal from an attached peripheral device in response to an external action request from an external source, thereby waking the computer and initializing device drivers to allow the peripheral device to perform predefined functions. During initiation of the power management system, the system provides a peripheral device with a PME_Status bit. In response to an external event, the peripheral device receives an external action request from the source of the external event. The peripheral device then sets the PME_Status bit and transmits a power management event (PME) signal to a computer operating system. Upon receiving the PME signal, the computer turns back on. The computer operating system then searches all peripheral devices connected to the computer for the set PME_Status bit.

Abstract: A process circuit is disclosed for computing a fast Fourier transform (FFT). In one embodiment, the processing circuit includes a memory device, a multiplier, a detector, a state machine, and a circuit for performing the 2's compliment of a coefficient. The memory storage device stores data values and coefficient (or twiddle) values. The detector integrates a date pointer with the state machine. The detector is designed to identify the symmetry lines (by memory address). The state machine, when notified by the detector that a line of symmetry has been encountered, appropriately adjusts either the coefficients, the imaginary sign, or the real sign for input to a multiplier.

Abstract: A two-stage op-amp circuit including a double-cascode telescopic op-amp circuit in the input stage and a fully-differential op-amp circuit in the output stage and having very high open-loop DC gain, very high unity-gain frequency, and relatively very low power consumption is presented. The input stage op-amp circuit and the output stage op-amp circuit are each comprised of a plurality of electrically connected MOSFET's. The input stage op-amp circuit provides very high gain, high input resistance, and large common mode rejection. The output stage op-amp circuit provides gain, low output resistance, and minimal output loss.

Abstract: In accordance with one aspect of the invention, an apparatus is provided for facilitating combined xDSL and POTS communication across a two wire pair. The apparatus includes a first communication port for communication with a central office across a two wire pair, and a second communication port for communication with a customer premises across a two wire pair. A splitter, or tap, is disposed at the first communication port for splitting a combined xDSL and POTS signal into a first and second signal path. A low pass filter is disposed in the first signal path for filtering the xDSL signal from the combined signal in the first signal path, leaving only the low-frequency (POTS frequency) signals. A circuit is disposed in the second signal path that is configured to filter the POTS signal from the combined signal, leaving only the xDSL signal.

Abstract: The present invention is directed to an improved direct memory access (DMA) controller for executing commands having an extremely compact structure, and which may be stored in an external memory. In accordance with one aspect of the present invention, a DMA controller is provided having circuitry configured to receive a memory segment, wherein the memory segment comprises a plurality of contiguous bytes from an external memory. The DMA controller also includes circuitry configured to parse the received memory segment into a plurality of distinct segments. The controller also includes circuitry configured to store the plurality of distinct segments into a plurality of internal registers, wherein the plurality of internal registers includes a command register. Finally, the DMA controller includes circuitry configured to decide the value stored in the command register to identify an instruction for execution.