Abstract: This circuit provides a scheme for protecting a common dynamic memory of a distributed processing system. This circuit protects against premature completion of a memory access cycle by a CPU for any of a number of fault conditions. As a result, common memory integrity is maintained despite a high number of memory accesses by a number of CPUs. This circuit operates in a simplex configuration or a duplicated redundant configuration.

Abstract: A digital multifrequency receiver circuit of the type employed between telephone system central offices, arranged to provide a faster response to received signals by processing the received signal tones digitally. The faster response resulting from the elimination of automatic gain control circuits and the use of a fixed gain amplifier used only when the received signal is below an acceptable level and the provision of a variable threshold to the individual frequency comparator circuits.

Abstract: A snubber circuit for use with hold circuits employed in telecommunication applications that employ an SCR as the principle control device. The included circuit prevents false hold turn on in response to static discharge. Voice band impedance and ringing signals are not adversely affected by the addition of the circuit to a standard SCR type hold circuit.

Abstract: A binary synchronous bit-sliced counter comprising a plurality of cascaded identical stages (slices). Each stage only requires for its operation a source of potential V.sub.dd, a carry-in signal input line, a clock signal input line, a reset signal input line and a carry-out signal output line. Cascading of the slices is implemented by connecting the carry-out signal output line of one slice to the carry-in signal input line of another slice and connecting the clock signal and reset signal input lines to all cascaded stages in parallel.

Abstract: The DTMF receiver sense and control arrangement collects and stores multiple customer originated data for determination of customer identification, validity and billing purposes. This arrangement is part of a telecommunications switching office and monitors up to 24 DTMF receivers (channels) to determine whether each channel contains valid data. This data is stored in temporary storage for subsequent transmission to a processor of the switching office. Each of the DTMF receivers asynchronously presents data for collection by this arrangement. This arrangement provides the proper timing required to operate up to 24 receivers to obtain their data, while it is stable at the receiver. Once a receiver transmits data, this arrangement then synchronizes its operation to that receiver so that, sequential monitoring of each of the 24 channels is guaranteed and no loss of valid data will result. In addition, each DTMF receiver may be enabled selectively for special monitoring.

Abstract: This invention is a cost efficient method for controlling a multistage space switching network for high voltage applications. This method minimizes the number of control signal leads required to operate a multistage space switching network. If a switching network has N space switching stages, then the present invention provides for performing the space switching function with N+1 control signal leads. The present space switching method may also be employed for conventional non-high voltage space switching applications.

Abstract: This invention is a cost efficient network arrangement for a space switching network for high voltage applications. This arrangement minimizes the number of control signal leads for a multistage switching network. If a switching network has N stages, then the present invention provides for performing the space switching operation with N+1 control signal leads. The present space switch arrangement may also be employed for conventional non-high voltage space switching applications.

Abstract: The DTMF receiver sense and control arrangement collects and stores multiple customer originated data for determination of customer identification, validity and billing purposes. This arrangement is part of a telecommunications switching office and monitors up to 24 DTMF receivers (channels) to determine whether each channel contains valid data. This data is stored in temporary storage for subsequent transmission to a processor of the switching office. Each of the DTMF receivers asynchronously presents data for collection by this arrangement. This arrangement provides the proper timing required to operate up to 24 receivers to obtain their data, while it is stable at the receiver. Once a receiver transmits data, this arrangement then synchronizes its operation to that receiver so that, sequential monitoring of each of the 24 channels is guaranteed and no loss of valid data will result. In addition, each DTMF receiver may be enabled selectively for special monitoring.

Abstract: A vented cap for covering an apparatus housing utilized in an outdoor environment including a pair of spaced apart roof panels defining therebetween a chamber. Apertures in the room panels out of registry with each other provide a path for ventilation of the enclosure while preventing the ingress of environmental elements such as rain. Mesas are raised above the surface of the inner roof panel and each contains one of the inner apertures. Drain apertures are formed around the periphery of the vented cap assist in permitting egress of environmental elements from and ingress of cooling air to the chamber.

Abstract: This invention is a cost efficient controller for a space switching network for high voltage applications. This controller is operated by a CPU which provides for generating a minimal number of control signals for a multistage space switching network. For a space switching network of N stages, the present controller generates N+1 control signals for operating the space switching function. The CPU of this controller is adaptable to implementation via a microprocessor CPU. The present controller arrangement may be also employed for conventional non-high voltage space switching applications.

Abstract: This invention describes a method for mapping one or more of a number of input events to one or more of a number of output functions. This method involves the use of a memory device to perform the mapping between the input events and the output functions. This invention performs the mapping function with a minimum of hardware devices.

Abstract: A connector for establishing connection between a printed wiring board and a ribbon-type cable through terminals on the printed wiring board and a corresponding contacts on the cable. The contacts are positioned to engage the terminals when the printed wiring board, the ribbon cable, and a resilient pad are compressed between a base and a frame. The frame is urged towards the base by clamps each including a handle pivoted about a pivot point on the frame acting to pull links, which are engaged with hooks attached to the base, toward the frame. Alignment pins are provided extending from the base towards the frame to position the pad and the ribbon cable and prevent their lateral motion relative to the base. A pair of alignment tongues extend from the base at an oblique angle and engage alignment bores in ears of the frame to maintain the frame in alignment with the base while providing wiping action for the contacts during engagement. A pair of handle locks retain the handles in an operated position.

Abstract: A phase comparator is included with each incoming channel to compare the clock phase of the incoming signal and a local oscillator. The phase comparator of an on-line active unit generates a signal to control the oscillator to maintain its output in phase with the incoming signal. The generated control signal is also connected to capacitor storage in associated channel phase comparators to provide them with an initial starting control voltage when they are switched in to be the receiving channels. Thus eliminating the uncontrolled operation of the oscillator during switching interval.

Abstract: A modulo 2.sup.2n -1 adder employing adders which may all be standard binary adders. A first binary adder sums binary input signals a and b to produce a first sum signal in which the n+2 more significant bits represent the integer part of (a+b)/2.sup.2n (i.e., of a+b taken modulo 2.sup.2n). A second binary adder subtracts these n+2 more significant bits from a 2n bit shifted (less significant bits) version thereof for producing a first difference signal which is subtracted from the first sum signal in a third binary adder to produce a binary signal R. The signal R is applied to one input of a fourth binary adder which produces the desired modulo 2.sup.2n -1 signal. A comparator circuit applies a constant (2.sup.2n -1) to a difference input of the fourth binary adder only when R is greater than or equal to this constant.

Abstract: A low insertion force arrangement for establishing a connection to a printed wiring board of the type including at least one printed wiring board terminal. The arrangement includes a plurality of connection springs including at least one actuator engaging area, and at least one pivot point, contact, and a terminal. A first embodiment includes an actuator engaging area located centrally on the spring between two pivot points which are located between a contact and a connection spring terminal. The actuator is a adapted to sequentially pivot a plurality of connection springs. A other embodiment includes at least one connection spring including a pivot point centrally located on the spring between an actuator engaging area and a second pivot point both of which are located between a contact and a connection spring terminal. In both embodiments the contact is located at one end of each connection spring in alignment with a corresponding printed wiring board terminal.

Abstract: An arrangement for constructing multi-layered printed circuits characterized by a first layer having top and bottom surfaces with the top surface including a plurality of parallel conductors divided into at least two conductor groups by a transversely oriented break across each conductor. The bottom surface further includes a plurality of parallel conductors arranged perpendicular to the conductors on the top surface and is also divided into at least two conductor groups by a transversely oriented break across each conductor. A plurality of holes extend through the first layer with, each hole adjacent to an intersecting conductor pair. A second layer including top and bottom surfaces and a plurality of plated-through holes has conductor pennants extending from selected holes in a first direction on the top surface and a second opposite direction on the bottom surface.

Abstract: A low insertion force connection arrangement for establishing a connection between at least two printed wiring boards each of the type including at least one printed wiring board terminal. The connection arrangement includes at least one connection spring including an actuator engaging area located centrally on a side of the spring facing the printed wiring boards and between two pivot points. The pivot points are located on a side of the connection spring facing away from the printed wiring boards and between two contacts. The contacts are located at opposite ends of the connection spring facing and in alignment with corresponding ones of the printed wiring board terminals.

Abstract: A low insertion force connection arrangement for establishing a connection between at least two printed wiring boards each of the type including a plurality of printed wiring board terminals. The connection arrangement includes a plurality of connection springs each including an actuator engaging area located centrally on a side of the spring facing the printed wiring boards and between two pivot points. The pivot points are located on a side of the connection spring facing away from the printed wiring boards and between two contacts. The contacts are located at opposite ends of the connection spring, facing, and in alignment with corresponding ones of the printed wiring board terminals.

Abstract: A low insertion force connection arrangement for establishing a connection between at least two printed wiring boards, each including a plurality of terminals. The connection arrangement includes a plurality of connection springs each having a pivot point facing away from the printed wiring boards and located between two actuator engaging areas. The actuator engaging areas face the printed wiring boards and are located between two contacts. The contacts are located at opposite ends of the connection spring facing and in alignment with a corresponding terminal of the printed wiring boards. A connector body is provided including a plurality of grooves each adapted to receive one of the printed wiring boards and a plurality of spring receiving cavities each enclosing a pair of connection springs.

Abstract: A control system for use in a condensation heating facility to control the secondary vapor blanket used to prevent loss of primary vapor. The control system includes a pair of secondary vapor sensors which detect a secondary vapor blanket slightly below and alternatively slightly above a design depth. The sensors are connected to control relays which energize a high rate dispensing pump to build the secondary vapor blanket when it is below the low depth and to energize a low rate dispensing pump when the secondary vapor blanket is between the low depth and the high depth. Additional control is arranged to inhibit dispensing of secondary liquid when the secondary vapor blanket is above the high depth or the primary vapor blanket is below its designed depth or finally during a vapor phase heating cycle where the primary and secondary vapor blankets collapse as a function of heating during the cycle.