Abstract: A level comparator is used to check the incoming message header pulse amplitude and if it is of a level higher than an established level a signal is transmitted to update a digital counter whose digital output is converted by a digital to analog converter to establish an increased analog reference level. If the incoming message header is lower the counter is decremented to establish a lower reference level. Then the levels of any signals present at fixed intervals after the header or sync pulse are measured and recorded. These measured levels constitute the value of correction required for subsequent pulses and are added to or subtracted from following data pulses as required.

Abstract: This invention is a circuit for detecting a framing pattern consisting of a pseudo random shift register sequence. This circuit utilizes an extremely long framing pattern without either a large amount of memory or the need to receive a large number of bits in order to recognize the framing pattern. The use of lengthy framing patterns minimizes the chance of false framing caused by patterns in bit positions other than the framing bit position. In addition, the incoming data stream may be connected directly to the shift register mechanism.

Abstract: A residue to analog converter associated with residue numbers {m1,m2,m3} of the residue number system defined by the moduli set {p1=2.sup.n -1, p2=2.sup.n, p3=2.sup.n +1} and which does not require memory comprises five standard binary adder circuits, apparatus for performing multiplication by bit shifting, and a modulo p1 p3 adder circuit. First and second binary adders combine the residue signals m1 and m3 to produce sum and difference signals which are bit shifted by grounding 2n-1 and n-1 lines, respectively, and locating them as less significant bit lines ahead of these sum and difference signal lines. A modulo p1*p3 adder sums these bit shifted signals. A third binary adder, which ignores overflow, performs a modulo p2=2.sup.n subtraction of m2 from the n less significant bits of the modulo p1*p3 sum signal to produce a second difference signal.

Abstract: A data entry and display control circuit for use in a telephone having a keypad and a plurality of features and pushbuttons. Each button can be programmed to execute one of the features. The telephone also includes a microprocessor and visual and audible prompting devices. These devices are operated by the microprocessor in response to prolonged operation of a selected pushbutton. Keypad initiated programming signals are then provided to both identify the feature to be assigned to the selected pushbutton and to control display functions. The microprocessor subsequently causes the assigned feature to be performed in response to momentary operation of the selected pushbutton. It also causes the cursor to move in response to the display function control signals.

Abstract: A method is disclosed for accomplishing modulo 2.sup.2n -1 addition with apparatus requiring adders that may be all standard binary adders. The method requires summing binary input signals a and b to produce a first sum signal in which the n+2 more significant bits thereof represent the integer part of a+b taken modulo 2.sup.2n. These n+2 more significant binary bits are subtracted from a 2n bit shifted product representation thereof for producing a first difference signal. This difference signal is subtracted from the first sum signal to produce a binary signal R. When R is greater than or equal to the constant (2.sup.2n -1), this constant is subtracted from the signal R for producing a binary signal that is the first sum signal a+b taken modulo 2.sup.2n -1 .

Abstract: In a signal measurement or processing system, specifically in a system which contemplates measurement or processing of video information and which is particularly adapted for use with microprocessors or microcomputers characterized by modest memory capacity and computational capability, a digital hysteresis circuit that enhances the quantization of an analog video signal. The hysteresis circuit is part of a transition detector that quantizes the brightness component of a composite video signal level into mutually exclusive and exhaustive BLACK and WHITE levels determined with regard to a THRESHOLD level. The THRESHOLD is established by applying a REFERENCE voltage, derived from the peak amplitude of the video signal, to a reference input of a D/A. The THRESHOLD is then established as a predetermined percentage of the REFERENCE voltage, as determined by a multibit digital CONTROL signal applied to the CONTROL input of the D/A.

Abstract: In a residue number system defined by the moduli set {p1=2.sup.n -1, p2=2.sup.n, p3=2.sup.n +1}, a method of converting residue number signals {m1,m2,m3} to associated analog signals r(m1,m2,m3), and that does not require memory devices, comprises the steps of generating a pair of binary signals that are the sum and difference of the residue numbers m1 and m3, bit shifting these sum and difference signals by inserting 2n-1 and n-1 binary 0's as less significant bits thereof, and summing these bit shifted signals modulo p1*p3 to produce a two dimensional binary signal r(m1,m3). A correction signal is generated by modulo p2=2.sup.n summing the n less significant bits of the signal r(m1,m3 ) and the negative of the residue signal m2 to produce a second difference signal, bit shifting this second difference signal by inserting 2n binary 0's as less significant bits thereof and subtracting the second difference signal from this bit shifted signal to produce the correction signal.

Abstract: In a residue number system defined by the moduli set {p1=2.sup.n -1, p2=2.sup.n, p3=2.sup.n +1}, a method of converting residue numbers {m1,m2,m3} to associated analog signals r(m1,m2,m3) comprises the steps of selecting a first binary signal satisfying the relationships .vertline.m1*S3+m3*S1.vertline..sub.p1*p3 (where the constant S1=p1*p2/2 and S3=p2*p3/2) from a first look-up table; and summing the n less significant bits of this first digital signal and the negative of the residue digit signal m2 in a first binary adder for generating a second binary signal that is representative of the difference therebetween, taken modulo p2. This second binary signal addresses a second look-up table containing third binary signals which correspond to possible values of the product of the second binary signal and p1 and p3. Selected first and third binary signals are summed in a second binary adder for producing a binary output signal r(m1,m2,m3) that is representative of the residue number {m1,m2,m3}.

Abstract: A circuit arranged to measure and correct for transmission line induced disturbances at discrete intervals after receipt of a header pulse by recording the presence of any voltage deviating from a set level. These levels are registered and during receipt of the data pulses are utilized at times corresponding to the relative position of the preceding data pulses to modify subsequent data bits.

Abstract: A residue to analog converter associated with residue numbers {m1,m2,m3} of the RNS defined by the moduli set {p1=2.sup.n -1, p2=2.sup.n, p3=2.sup.n +1} comprises a pair of ROMs and a pair of standard binary adders. The first ROM stores a look-up table of summations, taken modulo p1*p2, of possible values of m1*S3 and m3*S1 product terms, where S1=(p1*p2)/2 and S3=(p2*p3)/2, with associated memory locations being addressed by m1 and m3. The first binary adder performs a modulo 2.sup.n summation of a binary signal stored by the first ROM and -m2 by ignoring any overflow. The second ROM stores a look-up table of possible values of the products of p1, p3 and the modulo 2.sup.n signal. The second binary adder sums output signals of the two ROMs for producing a binary signal r(m1,m2,m3) that is representative of the residue signal {m1,m2,m3}. The corresponding analog signal is produced with a standard D/A converter.

Abstract: An FDM subscriber carrier system with two pilots located adjacent the upper and lower ends of the high frequency band uses the detected pilot levels at a repeater to adjust the gain and slope amplifiers in both directions of transmission. A microprocessor, programmed to identify the cable transmission characteristics, uses status signals derived from the two detected pilots to produce control signals to adjust and optimize the gain and slope settings of line amplifiers.

Abstract: A test set which tests coin trunk circuits for both normal and abnormal operations. A pair of light-emitting diodes monitor battery feed and reverse current. A first set of switch contacts simulate coin deposit while a second set of switch contacts connect fault, re-ring, coin deposit and coin return monitoring lamps and circuit paths to the coin trunk circuit.

Abstract: A leadless ceramic chip carrier for surface mounting on an epoxy printed circuit board is shown featuring an arrangement for relieving the thermally induced stress by progressively lengthening the attaching solder pillars as the distance from the center line of the ceramic chip increases to avoid exceeding the elastic limits of the solder.

Abstract: A circuit terminating clip for mechanically retaining and electrically connecting a planer substrate such as a thick/thin film circuit to a printed wiring card. The terminating clip is characterized by a terminating body having planer sidewalls defining a hollow interconnecting post receiving area therebetween. A substrate spring member extends from a bottom edge of a front wall of the terminating body arranged to accept the edge of the substrate, connecting the substrate to the terminating body. A terminating pad member extending from the top edge of the front wall of the terminating body is soldered to the substrate retaining the terminating body to the substrate. Post spring members extending inwardly into the post receiving area engage an interconnection post which extends from the printed wiring card thereby retaining the terminating body to the printed wiring card.

Abstract: An FDM subscriber carrier system with two pilots located adjacent the upper and lower ends of the high frequency band uses the detected pilot levels at a remote terminal to adjust the gain and slope amplifiers in both directions of transmission. A microprocessor, programmed to identify the cable transmission characteristics, uses status signals derived from the two detected pilots to produce control signals to adjust and optimize the gain and slope settings of line amplifiers.

Abstract: A circuit interconnection device for mechanically retaining and electrically connecting a planer substrate such as a thick/thin film circuit to a printed wiring card. The circuit interconnection device is characterized by a generally rectangular device body having planer sidewalls defining a hollow interconnection post receiving area therebetween. A pair of ears extend from a bottom edge of a front wall arranged to have an edge of the substrate rest thereon. A pair of substrate spring members extend outward from a top edge of the front wall to engage the substrate retaining and connecting the substrate to the terminating body. A rear wall includes a pair of post spring members extending inwardly into the post receiving area engaging an interconnection post extending from the printed wiring card thereby retaining and connecting the terminating body to the printed wiring card.

Abstract: In a 1.2 micron CMOS process, the gate oxide is formed by growing a 1000 Angstrom thickness of sacrificial oxide, immediately performing an oxide strip and then effecting a thin gate oxidation. The gate oxidation step is characterized by a temperature ramp from 700 to 950 degrees Centigrade in a flow of 9 liters per minute nitrogen and 0.36 liters per minute oxygen. At the 950 degrees Centigrade point, the nitrogen flow ceases and the oxygen flow increases to 9 liters per minute. The temperature is then downwardly ramped to 900 degrees Centigrade.

Abstract: A ring-ground circuit in a telephone system comprises a control transistor that selectively receives base drive from a microprocessor and that has its emitter connected through a low voltage LED and through the series combination of the base-emitter junction of a switching transistor and its emitter resistor to ground. The LED has a sharp transition in its conduction characteristics when the voltage across it reaches a predetermined value which is a reference voltage. Conduction of the control transistor provides base drive to the switching transistor for causing collector current in the latter to initiate a ground-start condition in a relay coil that is connected to a central office battery voltage. When current in the switching transistor increases to a prescribed value, that is set by the LED reference voltage and the emitter resistor, conduction of the switching transistor is automatically controlled for limiting the maximum value of its collector current.

Abstract: An electrical connector having a base portion duplicating a printed circuit card edge having thereon contacts for mating with a card jack to which is mounted a printed circuit card jack on the edge away from the contact surfaces. The card edge connector portion is plugged into a card jack of a test apparatus after which the attached card jack is the jack into which cards to be tested are inserted.

Abstract: An active current limiter in only the ring side of a telephone circuit has the control branch of a current mirror resistively connected across a supply voltage for establishing the magnitude of loop current in its other branch. A first resistor is also connected between adjacent one sides of the two branches for causing the control voltage and loop current to vary as a function of loop length. Extraneous metallic voltages on the A and B leads are AC coupled to associated inputs of a differential amplifier having its output connected through a second resistor to the one side of the control branch for modulating the loop current provided by the other branch. Opposite sides of the second resistor are fed back to associated input terminals of the amplifier. The amplitude modulated loop current is also fed back to an input of the amplifier for minimizing the affects of induced metallic voltages on the tip and ring lines.