Abstract: A display substrate includes: a base substrate; a first conductive pattern arranged on the base substrate; a first insulation layer arranged at a side of the first conductive pattern away from the base substrate; a second conductive pattern arranged at a side of the first insulation layer away from the base substrate; a second insulation layer arranged at a side of the second conductive pattern away from the base substrate; and a third conductive pattern arranged at a side of the second insulation layer away from the base substrate. The third conductive pattern and the first conductive pattern together serve as a first electrode plate of the capacitor, and the second conductive pattern serves as a second electrode plate of the capacitor.

Abstract: The display panel comprises a pixel driving circuit; the pixel driving circuit comprises a switching transistor; the display panel further comprises a base substrate, a first conductive layer, and a third conductive layer which are sequentially stacked; the first conductive layer is located on one side of the base substrate, and at least part of the first conductive layer is used for forming a gate of the switching transistor; the third conductive layer is located on the side of the first conductive layer facing away from the base substrate, the third conductive layer comprises a second signal line, and the second signal line is connected to the gate of the switching transistor by means of a via hole; the square resistance of the third conductive layer is less than the square resistance of the first conductive layer.

Abstract: A display panel has a display area including a plurality of pixel areas arranged in an array and a plurality of gate driving circuit areas. Each pixel area includes a pixel light-emitting sub-area and a pixel circuit sub-area arranged in a first direction. Pixel areas in each row correspond to at least two gate driving circuit areas each located between two adjacent pixel areas in this row. The display panel includes a gate driving circuit and a plurality of light-shielding portions. The gate driving circuit includes a plurality of shift registers that are cascaded. Each shift register includes a plurality of transistor groups, and each transistor group includes at least one transistor. Each light-shielding portion is located in a gate driving circuit area in which a transistor group is disposed, and is disposed on a periphery of the transistor group, and is electrically connected to a power supply signal line.

Abstract: A shift register, a gate drive circuit and a driving method therefor. The shift register includes a display pre-charge reset subcircuit, a sensing pre-charge reset subcircuit, a pull-down control subcircuit, an output subcircuit, a sensing cascade subcircuit and a black frame insertion cascade subcircuit. The display pre-charge reset subcircuit is configured to provide a signal of a first power supply end for a pull-up node under control of a first signal input end and provide a signal of a second power supply end to the pull-up node under control of a reset signal end; the sensing pre-charge reset subcircuit is configured to provide a signal of a first clock signal end to the pull-up node under control of the sensing cascade node and the first clock signal end, and provide a signal of the second power supply end to the pull-up node under control of a total reset end.

Abstract: A shift-register unit includes a first circuit including a first input circuit coupled via a first node to a first output circuit, and a second circuit including a second input circuit coupled via a second node to a second output circuit. The first input circuit is configured to control a voltage level of the first node in response to a first input signal. The first output circuit is configured to output a shift-register signal and a first output signal in response to the voltage level of the first node. The second input circuit is configured to control a voltage level of the second node in response to the first input signal. The second output circuit is configured to output a second output signal in response to the voltage level of the second node. The first input circuit and the second input circuit have a same circuit structure.

Abstract: A multiplexer circuit includes a first selection sub-circuit and a second selection sub-circuit. The first selection sub-circuit configured to transmit an input signal received at a input signal terminal to a first output terminal in response to a first control signal received at a first control terminal, and transmit a voltage of a power supply voltage terminal to the first output terminal in response to a second control signal received at a second control terminal. The second selection sub-circuit configured to transmit the input signal received at the input signal terminal to a second output terminal in response to a third control signal received at a third control terminal, and transmit the voltage of the power supply voltage terminal to the second output terminal in response to a fourth control signal received at a fourth control terminal.

Abstract: A shift register unit, a method for driving a shift register unit, a gate drive circuit, and a display device are disclosed. A shift register unit includes an input circuit, an output circuit, and a first control circuit. The input circuit controls a level of a first node in response to an input signal. The output circuit outputs at least one clock signal of at least one clock signal terminal to at least one signal output terminal under the control of the level of the first node, and outputs a level of a second node to at least one of the at least one signal output terminal in the case where the first node is at a non-operating potential. The first control circuit controls the level of the second node in response to the level of the first node.

Abstract: A shift register circuit includes: an input sub-circuit connected to a first node, and configured to receive a first control signal, and cause a potential of the first node to jump from an initial potential to a first potential greater than the initial potential; an output sub-circuit connected to the first node, and configured to receive a first clock signal, generate an output signal, cause the potential of the first node to jump from the first potential to a third potential greater than the first potential; and a chamfering sub-circuit connected to the first node, and configured to receive a second control signal, cause the potential of the first node to gradually decrease from the third potential to a fourth potential greater than the initial potential and less than the third potential, and cause the potential of the first node to jump from the fourth potential to the initial potential.

Abstract: A gate driving unit includes an Nth stage of shift register unit and an (N+1)th stage of shift register unit, N is a positive integer. The Nth stage of shift register unit includes an Nth stage of pull-up node control circuit, and the (N+1)th stage of shift register unit includes an (N+1)th stage of pull-up node control circuit. The Nth stage of pull-up node control circuit is electrically connected to an Nth stage of pull-up node and a control line, controls a potential of the Nth stage of pull-up node under the control of a control signal inputted by the control line. The (N+1)th stage of pull-up node control circuit is electrically connected to an (N+1)th stage of pull-up node and the control line, respectively, and controls a potential of the (N+1)th stage of pull-up node under the control of the control signal inputted by the control line.

Abstract: A shift register unit and a control method thereof, a gate driving circuit and a control method thereof, and a display apparatus are provided. The shift register unit includes: a first shift register coupled to an input signal terminal, a first clock signal terminal and a second clock signal terminal. The first shift register is configured to generate a first output signal based on the signal at the first clock signal terminal and generate a second output signal based on the signal at the second clock signal terminal; and a second shift register coupled to the input signal terminal and a third clock signal terminal, the second shift register is configured to generate a third output signal based on the signal at the third clock signal terminal. The first shift register includes a first control circuit, a first output circuit and a second output circuit.

Abstract: The present disclosure provides a display panel and a display device. The display panel includes a gate driving circuit including a first transistor; a base substrate; a functional layer located on a side of the base substrate, a material of the functional layer is a thermal conductive material, and the functional layer includes a first functional portion; an active layer located on a side of the functional layer away from the base substrate, the active layer includes a first active portion including at least one first active sub-portion which is configured to form a channel region of the first transistor; a second conductive layer located on a side of the active layer away from the base substrate, the second conductive layer includes a first conductive portion connected to the first functional portion through a first via hole.

Abstract: A shift-register unit includes a first circuit including a first input circuit coupled via a first node to a first output circuit, and a second circuit including a second input circuit coupled via a second node to a second output circuit. The first input circuit is configured to control a voltage level of the first node in response to a first input signal. The first output circuit is configured to output a shift-register signal and a first output signal in response to the voltage level of the first node. The second input circuit is configured to control a voltage level of the second node in response to the first input signal. The second output circuit is configured to output a second output signal in response to the voltage level of the second node. The first input circuit and the second input circuit have a same circuit structure.

Abstract: Provided is a method for driving a display device including n rows of sub-pixels; the method includes: driving the first frame of image, including: performing normal display driving on the n rows of sub-pixels in a display driving period, performing darkness insertion driving on a rows, from the 1st to ath rows, of sub-pixels in a first darkness insertion sub-period, and performing darkness insertion driving on (n?a) rows, from the (a+1)th to nth rows, of sub-pixels in a second darkness insertion sub-period driving a second frame of image, including: performing normal display driving on the n rows of sub-pixels in a display driving period, performing darkness insertion driving on b rows, from the 1st to bth rows, of sub-pixels in a first darkness insertion sub-period, and performing darkness insertion driving on (n?b) rows, from the (b+1)th to nth rows, of sub-pixels in a second darkness insertion sub-period.

Abstract: Provided are a display panel and a manufacturing method thereof, and a display device. The display panel includes: a base substrate; anodes and a mark pattern including at least one first mark pattern; a pixel defining layer having openings, wherein the orthographic projection of each opening on the base substrate at least partially overlaps with that of a corresponding anode, and the orthographic projection of the mark pattern on the base substrate is located within that of the pixel defining layer; at least one group of ink droplets including one or more ink droplets, and the orthographic projection of each ink droplet on the base substrate is located within that of the pixel defining layer; a functional layer including at least one sub-layer including a light-emitting layer, and the material of each group of ink droplets is the same as that of a sub-layer; and a cathode.

Abstract: A shift register unit, a driving method thereof, and a gate driving circuit are disclosed. The shift register unit includes: an input circuit configured to receive an input signal from an input signal terminal and output the input signal to a voltage stabilizer node; a voltage-stabilizing circuit configured to input potential of the voltage stabilizer node to a pull-up node and control potential of the voltage stabilizer node; an output circuit configured to receive a clock signal from a clock signal terminal and provide an output signal to an output signal terminal based on the clock signal received under control of the potential of the pull-up node; and a control circuit configured to control potential of the output signal terminal under control of the potential of the pull-up node.

Abstract: A pixel circuit includes a data line, a sensing line, a first pixel sub-circuit and a second pixel sub-circuit. The first pixel sub-circuit includes a first writing unit, a first sensing unit and a first driving unit. The first driving unit is configured to drive a first light-emitting unit to emit light. The second pixel sub-circuit includes a second writing unit, a second sensing unit and a second driving unit. The second driving unit is configured to drive a second light-emitting unit to emit light. The first writing unit and the second sensing unit are both configured to be connected to a gate driving unit. The second writing unit and the first sensing unit are both configured to be connected to another gate driving unit.

Abstract: The present disclosure provides a defining solution for preparing a pixel defining layer configured to define individual pixels on a substrate, comprising: a lyophilic material, a lyophobic material and an initiator, wherein the lyophobic material comprises: a first lyophobic material and a second lyophobic material, and wherein a mass average molecular weight of the first lyophobic material is greater than a mass average molecular weight of the second lyophobic material, and a mass average molecular weight of the lyophilic material is greater than the mass average molecular weight of the first lyophobic material. The present disclosure further provides a display panel, a display apparatus and a method of preparing a pixel defining layer.

Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are provided. The shift register unit includes an input circuit, a first control circuit, a blanking control circuit, a first output circuit, and a second output circuit. The input circuit is configured to control a level of a first node in response to an input signal input; the first control circuit is configured to control a level of the second node; the blanking control circuit is configured to control the level of the first node and the level of the second node; the first output circuit is configured to output a first output signal at the first output terminal under control of the level of the first node; and the second output circuit is configured to output a second output signal at the second output terminal under control of the level of the second node.

Abstract: The present disclosure relates to the field of display technology, and describes a pixel driving circuit detection method, a display panel, a driving method thereof, and a display device. The detection method includes inputting a reference voltage to the data line during at least part of the initial phase; turning on the first and second switch sub-circuits during the charging phase, to input the detection voltage to the data line, while inputting the reset voltage to the sensing line; turning on the second switch sub-circuit during the charging phase, to input the driving current by the driving transistor to the sensing line under the effect of the detection voltage; turning off the first and second switch sub-circuits during the detection phase, to detect the voltage on the sensing line; and obtaining the mobility of the driving transistor according to the voltage on the sensing line detected in the detection phase.

Abstract: The present disclosure provides a shift resister unit, a gate driving circuit, a display device, and a method for controlling a shift register unit. The shift register unit incudes a first input sub-circuit, a first output sub-circuit, a first reset sub-circuit, a second input sub-circuit, and a third input sub-circuit. The first input sub-circuit is configured to change a potential of a first node in a first phase. The first output sub-circuit is configured to output a gate driving signal in the first phase and output a compensation driving signal in a second phase. The first reset sub-circuit is configured to reset the first node. The second input sub-circuit is configured to change a potential of a second node in the first phase and maintain the potential of the second node. The third input sub-circuit is configured to change the potential of the first node in the second phase.