Patents Assigned to Hefei Core Storage Electronics Limited
  • Patent number: 11983415
    Abstract: A memory management method for a memory storage device is provided. The memory management method includes: detecting effective information of at least one operation event performed by the memory storage device in a first mode; and adjusting a threshold value according to the effective information. The threshold value is configured to determine whether to instruct the memory storage device to enter the first mode.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: May 14, 2024
    Assignee: Hefei Core Storage Electronic Limited
    Inventors: Qi-Ao Zhu, Chong Peng, Zhi Wang, Wan-Jun Hong
  • Patent number: 11954020
    Abstract: A memory adaptive temperature controlling method, a storage device, and a control circuit unit are provided. In this exemplary embodiment, the temperature value is obtained according to the temperature measured by the thermal sensor, and the access speed to be reached is calculated according to the temperature change rate within the specific time range and the adjustment percentage when it is determined that the speed-down or speed-up operation is required to be performed. By adjusting the access speed of the memory storage device in a stepwise manner, the temperature of the memory storage device may be stabilized, thereby striking the balance between the temperature stability and the system performance of the memory storage device.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: April 9, 2024
    Assignee: Hefei Core Storage Electronics Limited
    Inventors: Chih-Ling Wang, Qi-Ao Zhu, Xu Hui Cheng
  • Publication number: 20240028506
    Abstract: A mapping table re-building method, a memory storage device and a memory control circuit unit are disclosed. The method includes: receiving write command from a host system, wherein the write command instructs storing first data to a first logical unit; performing a programming operation according to the write command to store the first data and identification information of the first logical unit to a first physical unit; updating a mapping table in response to the programming operation; detecting a table abnormal event related to the mapping table; reading the identification information of the first logical unit from the first physical unit in response to the table abnormal event; and re-building the mapping table according to the identification information of the first logical unit.
    Type: Application
    Filed: August 8, 2022
    Publication date: January 25, 2024
    Applicant: Hefei Core Storage Electronic Limited
    Inventors: Chih-Ling Wang, Qi-Ao Zhu, Yuting Niu, Yang Zhang
  • Patent number: 11822798
    Abstract: A data storing allocation method, a memory storage apparatus, and a memory control circuit unit are provided. The method includes the following. A plurality of data writing speeds of a plurality of memory units are detected. An initial write volume of each memory unit is determined according to a number of dies in each memory unit. At least one compensation data volume is calculated according to the data writing speeds and the initial write volume of each memory unit. A write data corresponding to a write command is written to the memory units according to the initial write volume of each memory unit and the at least one compensation data volume.
    Type: Grant
    Filed: December 19, 2021
    Date of Patent: November 21, 2023
    Assignee: Hefei Core Storage Electronic Limited
    Inventors: Qi-Ao Zhu, Jing Zhang, Kuai Cao, Xin Wang
  • Patent number: 11817172
    Abstract: A table management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: storing multiple table groups, wherein each of the table groups includes multiple voltage management tables; detecting a status of the memory storage device; determining one of the table groups as a target table group according to the status of the memory storage device, wherein the target table group includes multiple target voltage management tables; reading data from a rewritable non-volatile memory module by using at least one read voltage level according to at least one of the target voltage management tables.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: November 14, 2023
    Assignee: Hefei Core Storage Electronic Limited
    Inventors: Chih-Ling Wang, Qi-Ao Zhu, Jing Zhang, Yang Zhang
  • Publication number: 20230359357
    Abstract: A write control method based on write behavior prediction, a memory storage device, and a memory control circuit unit are provided. The method includes: monitoring a first data write behavior of a host system during a first time range; according to the first data write behavior, predicting a second data write behavior of the host system during a second time range; obtaining a first measurement parameter and a first target parameter corresponding to the first data write behavior; according to the first measurement parameter, the first target parameter, and the second data write behavior, determining a write control parameter; and sending a write command sequence according to the write control parameter to instruct a rewritable non-volatile memory module to perform a data write based on multiple write modes during the second time range.
    Type: Application
    Filed: May 17, 2022
    Publication date: November 9, 2023
    Applicant: Hefei Core Storage Electronic Limited
    Inventors: Chih-Ling Wang, FAN YI, Kuai Cao, Yang Chen, Qin Qin Tao, Dong Sheng Rao
  • Patent number: 11803208
    Abstract: A timer calibration method and an electronic device are disclosed. The method includes: performing a fitting operation according to a clock frequency of a clock device and an output of a timer to generate a fitting function; obtaining a first value output by the timer; and adjusting the first value to be a second value according to the fitting function to calibrate the timer.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: October 31, 2023
    Assignee: Hefei Core Storage Electronic Limited
    Inventors: Yang Chen, Yue Hu, Dong Sheng Rao, Kuai Cao, Qin Qin Tao
  • Patent number: 11803331
    Abstract: A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: performing a first write operation to store first data to a first physical unit; recording first unit management information corresponding to the first write operation, wherein the first unit management information reflects a usage order of first used physical units, and the first used physical units include the first physical unit; performing data merge operation to copy at least a part of data stored in the first physical unit to a second physical unit; and after the data merge operation is performed, recording second unit management information according to the first unit management information, wherein the second unit management information reflects a usage order of second used physical units. The second used physical units include the second physical unit but do not include the first physical unit.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: October 31, 2023
    Assignee: Hefei Core Storage Electronic Limited
    Inventors: Wan-Jun Hong, Yang Zhang, Wenbin Tao, Hao Yang, Mengkai Wu, Yankai Dai
  • Publication number: 20230325310
    Abstract: A memory adaptive temperature controlling method, a storage device, and a control circuit unit are provided.
    Type: Application
    Filed: May 9, 2022
    Publication date: October 12, 2023
    Applicant: Hefei Core Storage Electronic Limited
    Inventors: Chih-Ling Wang, Qi-Ao Zhu, Xu Hui Cheng
  • Publication number: 20230326502
    Abstract: A table management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: storing multiple table groups, wherein each of the table groups includes multiple voltage management tables; detecting a status of the memory storage device; determining one of the table groups as a target table group according to the status of the memory storage device, wherein the target table group includes multiple target voltage management tables; reading data from a rewritable non-volatile memory module by using at least one read voltage level according to at least one of the target voltage management tables.
    Type: Application
    Filed: April 29, 2022
    Publication date: October 12, 2023
    Applicant: Hefei Core Storage Electronic Limited
    Inventors: Chih-Ling Wang, Qi-Ao Zhu, Jing Zhang, Yang Zhang
  • Publication number: 20230297232
    Abstract: A table sorting method, a memory storage device, and a memory control circuit unit are provided. The method includes: reading first data from a first physical unit by using a first read voltage level according to a first voltage management table among multiple voltage management tables; decoding the first data; in response to the first data being successfully decoded, updating count information corresponding to the first voltage management table; and in response to the count information meeting a default condition, increasing a usage priority of the first voltage management table among the voltage management tables.
    Type: Application
    Filed: April 11, 2022
    Publication date: September 21, 2023
    Applicant: Hefei Core Storage Electronic Limited
    Inventors: Chih-Ling Wang, Qi-Ao Zhu, Jing Zhang, Jian Hu
  • Patent number: 11748026
    Abstract: A mapping information recording method for a rewritable non-volatile memory module is provided. The rewritable non-volatile memory module includes multiple physical erasing units, and each of the physical erasing unit includes multiple physical programming units. The mapping information recording method includes: receiving first continuous data from a host system, wherein the host system instructs to store the first continuous data to a first continuous logical address; establishing a continuous mapping table to record a start logical address of the first continuous logical address, a length of the first continuous logical address, and a bitmap; writing the first continuous data into first physical programming units; and marking bits of virtual blocks corresponding to the first continuous logical address in the bitmap as a valid state, numbering the virtual blocks, and recording the numbers into the continuous mapping table.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: September 5, 2023
    Assignee: Hefei Core Storage Electronic Limited
    Inventors: Qi-Ao Zhu, Jing Zhang
  • Patent number: 11715532
    Abstract: A risk assessment method based on data priority, a memory storage device, and a memory control circuit unit are provided. The method includes: receiving a query command from a host system; in response to the query command, performing a data health detection on a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module stores data with multiple data priorities; generating risk assessment information according to a detection result, wherein the risk assessment information reflects a health degree of data with different data priorities in the rewritable non-volatile memory modules by different risk levels; and transmitting the risk assessment information to the host system.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: August 1, 2023
    Assignee: Hefei Core Storage Electronic Limited
    Inventors: Chih-Ling Wang, Yue Hu, Qin Qin Tao, Dong Sheng Rao, Shao Feng Yang, Yang Chen
  • Patent number: 11693567
    Abstract: A memory performance optimization method, a memory control circuit unit, and a memory storage device are provided. The method includes the following. An idle time of the memory storage device is counted in an active mode. The memory storage device is instructed to enter a first low electricity consumption mode from the active mode in response to the idle time being greater than an idle threshold. A first waiting time of the memory storage device is counted in the first low electricity consumption mode. The memory storage device is instructed to enter a second low electricity consumption mode from the first low electricity consumption mode in response to the first waiting time being greater than a first waiting threshold. Electricity consumption of the second low electricity consumption mode is lower than electricity consumption of the first low electricity consumption mode.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: July 4, 2023
    Assignee: Hefei Core Storage Electronic Limited
    Inventors: Qi-Ao Zhu, Jing Zhang, Kuai Cao, Xin Wang, Xu Hui Cheng, Dong Sheng Rao
  • Publication number: 20230205451
    Abstract: A multi-channel memory storage device, a memory control circuit unit, and a data reading method are provided. The method includes: determining whether a storage space of a buffer memory is insufficient when a multi-channel access is performed; issuing a data read command corresponding to each of a plurality of multi-channels to a rewritable non-volatile memory module according to a logical address in a host read command in response to insufficient storage space of the buffer memory to read data corresponding to each of the plurality of multi-channels from a data storage area to a data cache area via the plurality of multi-channels; and allocating the storage space of the buffer memory to the rewritable non-volatile memory module after the storage space of the buffer memory is released and issuing a cache read command to move first data in data temporarily stored in the data cache area to the buffer memory.
    Type: Application
    Filed: January 19, 2022
    Publication date: June 29, 2023
    Applicant: Hefei Core Storage Electronic Limited
    Inventors: Wan-Jun Hong, Qi-Ao Zhu, Xin Wang, Yang Zhang, Xu Hui Cheng, Jian Hu
  • Publication number: 20230185329
    Abstract: A timer calibration method and an electronic device are disclosed. The method includes: performing a fitting operation according to a clock frequency of a clock device and an output of a timer to generate a fitting function; obtaining a first value output by the timer; and adjusting the first value to be a second value according to the fitting function to calibrate the timer.
    Type: Application
    Filed: January 11, 2022
    Publication date: June 15, 2023
    Applicant: Hefei Core Storage Electronic Limited
    Inventors: Yang Chen, Yue Hu, Dong Sheng Rao, Kuai Cao, Qin Qin Tao
  • Publication number: 20230176782
    Abstract: A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: performing a first write operation to store first data to a first physical unit; recording first unit management information corresponding to the first write operation, wherein the first unit management information reflects a usage order of first used physical units, and the first used physical units include the first physical unit; performing data merge operation to copy at least a part of data stored in the first physical unit to a second physical unit; and after the data merge operation is performed, recording second unit management information according to the first unit management information, wherein the second unit management information reflects a usage order of second used physical units. The second used physical units include the second physical unit but do not include the first physical unit.
    Type: Application
    Filed: December 29, 2021
    Publication date: June 8, 2023
    Applicant: Hefei Core Storage Electronic Limited
    Inventors: Wan-Jun Hong, Yang Zhang, Wenbin Tao, Hao Yang, Mengkai Wu, Yankai Dai
  • Patent number: 11669270
    Abstract: A multi-channel memory storage device, a memory control circuit unit, and a data reading method are provided. The method includes: determining whether a storage space of a buffer memory is insufficient when a multi-channel access is performed; issuing a data read command corresponding to each of a plurality of multi-channels to a rewritable non-volatile memory module according to a logical address in a host read command in response to insufficient storage space of the buffer memory to read data corresponding to each of the plurality of multi-channels from a data storage area to a data cache area via the plurality of multi-channels; and allocating the storage space of the buffer memory to the rewritable non-volatile memory module after the storage space of the buffer memory is released and issuing a cache read command to move first data in data temporarily stored in the data cache area to the buffer memory.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: June 6, 2023
    Assignee: Hefei Core Storage Electronic Limited
    Inventors: Wan-Jun Hong, Qi-Ao Zhu, Xin Wang, Yang Zhang, Xu Hui Cheng, Jian Hu
  • Publication number: 20230132837
    Abstract: A mapping information recording method for a rewritable non-volatile memory module is provided. The rewritable non-volatile memory module includes multiple physical erasing units, and each of the physical erasing unit includes multiple physical programming units. The mapping information recording method includes: receiving first continuous data from a host system, wherein the host system instructs to store the first continuous data to a first continuous logical address; establishing a continuous mapping table to record a start logical address of the first continuous logical address, a length of the first continuous logical address, and a bitmap; writing the first continuous data into first physical programming units; and marking bits of virtual blocks corresponding to the first continuous logical address in the bitmap as a valid state, numbering the virtual blocks, and recording the numbers into the continuous mapping table.
    Type: Application
    Filed: December 16, 2021
    Publication date: May 4, 2023
    Applicant: Hefei Core Storage Electronic Limited
    Inventors: Qi-Ao Zhu, Jing Zhang
  • Publication number: 20230127512
    Abstract: A memory performance optimization method, a memory control circuit unit, and a memory storage device are provided. The method includes the following. An idle time of the memory storage device is counted in an active mode. The memory storage device is instructed to enter a first low electricity consumption mode from the active mode in response to the idle time being greater than an idle threshold. A first waiting time of the memory storage device is counted in the first low electricity consumption mode. The memory storage device is instructed to enter a second low electricity consumption mode from the first low electricity consumption mode in response to the first waiting time being greater than a first waiting threshold. Electricity consumption of the second low electricity consumption mode is lower than electricity consumption of the first low electricity consumption mode.
    Type: Application
    Filed: November 22, 2021
    Publication date: April 27, 2023
    Applicant: Hefei Core Storage Electronic Limited
    Inventors: Qi-Ao Zhu, Jing Zhang, Kuai Cao, Xin Wang, Xu Hui Cheng, Dong Sheng Rao