Patents Assigned to Hefei Core Storage Electronics Limited
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Patent number: 11635460Abstract: A memory temperature controlling method and a memory temperature controlling system are provided. The method includes: performing, by a testing equipment, test modes on a memory storage device, and obtaining a first internal temperature of a memory control circuit unit, a second internal temperature of each memory package and a surface temperature of each memory package to establish a linear relationship expression of the first internal temperature, the second internal temperature and the surface temperature; using, by the memory storage device, the linear relationship expression to calculate a predicted surface temperature of a rewritable non-volatile memory based on a first current internal temperature of the memory control circuit unit and a second current internal temperature of each memory package; adjusting, by the memory storage device, an operating frequency for accessing the rewritable non-volatile memory based on the predicted surface temperature.Type: GrantFiled: September 27, 2021Date of Patent: April 25, 2023Assignee: Hefei Core Storage Electronic LimitedInventors: Biao Zhang, Weikang Wang, Hai Han, Jun Liang, Ren Jun Tang
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Patent number: 11620072Abstract: A memory management method, a memory control circuit unit and a memory storage apparatus are provided. The method includes: recording a valid count of each physical erasing unit in a plurality of physical erasing units; sequentially arranging M physical erasing units corresponding to each of chip enable groups according to the valid count to form a plurality of sorted physical erasing units; remapping the physical erasing units corresponding to M virtual blocks according to the plurality of sorted physical erasing units; calculating a total number of valid counts of the remapped M virtual blocks, and sequentially arranging the remapped M virtual blocks according to the total number of valid counts to form a plurality of sorted virtual blocks; and sequentially extracting at least one of the sorted virtual blocks as a source virtual block to perform a garbage collection operation.Type: GrantFiled: May 5, 2021Date of Patent: April 4, 2023Assignee: Hefei Core Storage Electronic LimitedInventor: Chong Peng
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Publication number: 20230098366Abstract: A memory polling method, a memory storage device and a memory control circuit unit are provided. The memory polling method includes: detecting a plurality of busy times corresponding to a plurality of physical units when executing a plurality of first commands; counting the busy times corresponding to the physical units to generate a count statistic value, and determine a delay time based on the count statistic value; and transmitting a plurality of status requests to a rewritable non-volatile memory module after the delay time.Type: ApplicationFiled: October 13, 2021Publication date: March 30, 2023Applicant: Hefei Core Storage Electronic LimitedInventors: Qi-Ao Zhu, Jing Zhang, Kuai Cao, Xin Wang, Xu Hui Cheng, Wan-Jun Hong
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Publication number: 20230076481Abstract: A memory thermal throttling method and a memory thermal throttling system are provided. The method includes: performing, by a testing equipment, test modes on a memory storage device, and obtaining an internal temperature of a memory control circuit unit, a work loading of each memory package and a surface temperature of each memory package to establish a linear relationship between the work loading, the internal temperature, and the surface temperature; storing, by the testing equipment, the linear relationship in the memory storage device; using, by the memory storage device, the linear relationship based on a current internal temperature of the memory control circuit unit and a current work loading of a first memory package of the memory packages to calculate a predicted surface temperature of the first memory package; adjusting, by the memory storage device, an operating frequency for accessing the first memory package based on the predicted surface temperature.Type: ApplicationFiled: September 27, 2021Publication date: March 9, 2023Applicant: Hefei Core Storage Electronic LimitedInventors: Ren Jun Tang, Weikang Wang, Hai Han, Jun Liang, Biao Zhang
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Publication number: 20230074401Abstract: A memory temperature controlling method and a memory temperature controlling system are provided. The method includes: performing, by a testing equipment, test modes on a memory storage device, and obtaining a first internal temperature of a memory control circuit unit, a second internal temperature of each memory package and a surface temperature of each memory package to establish a linear relationship expression of the first internal temperature, the second internal temperature and the surface temperature; using, by the memory storage device, the linear relationship expression to calculate a predicted surface temperature of a rewritable non-volatile memory based on a first current internal temperature of the memory control circuit unit and a second current internal temperature of each memory package; adjusting, by the memory storage device, an operating frequency for accessing the rewritable non-volatile memory based on the predicted surface temperature.Type: ApplicationFiled: September 27, 2021Publication date: March 9, 2023Applicant: Hefei Core Storage Electronic LimitedInventors: Biao Zhang, Weikang Wang, Hai Han, Jun Liang, Ren Jun Tang
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Patent number: 11586364Abstract: A memory management method is provided according to the invention. The method includes: reading a physical unit and updating a read count of the physical unit; scanning the physical unit if the updated read count is not less than a read count threshold; and adjusting the read count threshold according to the read count and a read error bit. Therefore, a data unit that needs to be scanned can be determined to reduce unnecessary data scanning.Type: GrantFiled: February 3, 2020Date of Patent: February 21, 2023Assignee: Hefei Core Storage Electronic LimitedInventors: Xin Hu, Liang Xu, Xiaoyang Zhang, Zhi Wang
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Patent number: 11573908Abstract: A mapping table management method, a memory control circuit unit, and a memory storage device are provided. The method includes: receiving a read command from a host system, wherein the read command indicates reading a first data stored in at least one first logical address; and searching whether a relation management information reflects that a first group static mapping table recording the first logical address is related to a dynamic mapping table. In response to a search result reflecting that the first group static mapping table is related to the dynamic mapping table, the dynamic mapping table is searched to obtain a first physical address mapped by the first logical address. And if not related, the first group static mapping table among group static mapping tables is searched to obtain a second physical address mapped by the first logical address.Type: GrantFiled: January 23, 2022Date of Patent: February 7, 2023Assignee: Hefei Core Storage Electronic LimitedInventor: Chong Peng
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Publication number: 20220326871Abstract: A memory management method, a memory control circuit unit and a memory storage apparatus are provided. The method includes: recording a valid count of each physical erasing unit in a plurality of physical erasing units; sequentially arranging M physical erasing units corresponding to each of chip enable groups according to the valid count to form a plurality of sorted physical erasing units; remapping the physical erasing units corresponding to M virtual blocks according to the plurality of sorted physical erasing units; calculating a total number of valid counts of the remapped M virtual blocks, and sequentially arranging the remapped M virtual blocks according to the total number of valid counts to form a plurality of sorted virtual blocks; and sequentially extracting at least one of the sorted virtual blocks as a source virtual block to perform a garbage collection operation.Type: ApplicationFiled: May 5, 2021Publication date: October 13, 2022Applicant: Hefei Core Storage Electronic LimitedInventor: Chong Peng
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Publication number: 20220291862Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The memory management method includes: storing first management information in a rewritable non-volatile memory module, wherein the first management information reflects a storage status of abnormal data in a first physical unit in the rewritable non-volatile memory module; receiving a read command from a host system, wherein the read command instructs to read data stored in a logical unit corresponding to a physical node in the first physical unit; inquiring the first management information according to the read command; transmitting data read from the physical node to the host system if an inquiring result reflects that the abnormal data is not stored in the physical node; and transmitting error information to the host system if the inquiring result reflects that the abnormal data is stored in the physical node.Type: ApplicationFiled: March 21, 2021Publication date: September 15, 2022Applicant: Hefei Core Storage Electronic LimitedInventors: Yan Zheng, Zhi Wang, Kai-Di Zhu
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Patent number: 11442657Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The memory management method includes: storing first management information in a rewritable non-volatile memory module, wherein the first management information reflects a storage status of abnormal data in a first physical unit in the rewritable non-volatile memory module; receiving a read command from a host system, wherein the read command instructs to read data stored in a logical unit corresponding to a physical node in the first physical unit; inquiring the first management information according to the read command; transmitting data read from the physical node to the host system if an inquiring result reflects that the abnormal data is not stored in the physical node; and transmitting error information to the host system if the inquiring result reflects that the abnormal data is stored in the physical node.Type: GrantFiled: March 21, 2021Date of Patent: September 13, 2022Assignee: Hefei Core Storage Electronic LimitedInventors: Yan Zheng, Zhi Wang, Kai-Di Zhu
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Patent number: 11341039Abstract: A data arrangement method of a flash memory, a flash memory storage device, and a flash memory control circuit unit are provided. The method may be applied to a flash memory, an embedded memory device, or a solid-state disk having a three-dimensional (3D) structure. The method includes: executing a background garbage collection operation in a background mode; receiving at least one write command from a host when the background garbage collection operation is not completed to suspend the background garbage collection operation and exit the background mode; executing the at least one write command; and entering the background mode and continuing the execution of the background garbage collection operation after the at least one write command is completed. Therefore, execution efficiency of the write command in a foreground mode may be optimized.Type: GrantFiled: April 17, 2020Date of Patent: May 24, 2022Assignee: Hefei Core Storage Electronic LimitedInventors: Zhi Wang, Yan Zheng, Xiaoyang Zhang, Kai-Di Zhu
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Patent number: 11281402Abstract: A memory management method. The memory management method includes: receiving a command from a host system; sending a command sequence corresponding to the command to a rewritable non-volatile memory module; determining a delay time; and sending a plurality of polling commands to the rewritable non-volatile memory module after the delay time.Type: GrantFiled: January 22, 2020Date of Patent: March 22, 2022Assignee: Hefei Core Storage Electronic LimitedInventors: Qi-Ao Zhu, Jing Zhang, Wan-Jun Hong, Ya-Lin Zhu, Tong-Jin Liu
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Patent number: 11221791Abstract: A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: receiving a first write command from a host system; instructing a rewritable non-volatile memory module to perform a first write operation according to the first write command; obtaining first performance information corresponding to the first write operation; and updating threshold information according to the first performance information, wherein the threshold information is configured to determine a type of target data.Type: GrantFiled: August 22, 2019Date of Patent: January 11, 2022Assignee: Hefei Core Storage Electronic LimitedInventors: Qi-Ao Zhu, Jing Zhang, Xin Wang, Kai-Di Zhu
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Patent number: 11175847Abstract: A data merging method for flash memory, a flash memory control circuit unit and a flash memory storage device are provided. The disclosure is applicable to a flash memory, an embedded memory device or a solid state drive of 3D structure. The method includes: selecting at least one source physical erasing unit from at least one first physical erasing unit according to a valid data count of the at least one first physical erasing unit and a valid data count of each of a plurality of memory sub-modules; and copying valid data in the at least one source physical erasing unit to at least one destination physical erasing unit to perform a valid data merging operation.Type: GrantFiled: March 18, 2020Date of Patent: November 16, 2021Assignee: Hefei Core Storage Electronic LimitedInventors: Qi-Ao Zhu, Wan-Jun Hong, Jing Zhang, Xin Wang, Xu Hui Cheng
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Publication number: 20210294737Abstract: A data arrangement method of a flash memory, a flash memory storage device, and a flash memory control circuit unit are provided. The method may be applied to a flash memory, an embedded memory device, or a solid-state disk having a three-dimensional (3D) structure. The method includes: executing a background garbage collection operation in a background mode; receiving at least one write command from a host when the background garbage collection operation is not completed to suspend the background garbage collection operation and exit the background mode; executing the at least one write command; and entering the background mode and continuing the execution of the background garbage collection operation after the at least one write command is completed. Therefore, execution efficiency of the write command in a foreground mode may be optimized.Type: ApplicationFiled: April 17, 2020Publication date: September 23, 2021Applicant: Hefei Core Storage Electronic LimitedInventors: Zhi Wang, Yan Zheng, Xiaoyang Zhang, Kai-Di Zhu
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Patent number: 11087848Abstract: A data arranging method, a memory control circuit unit and a memory storage device for flash memory are provided. The method can be applied to a flash memory with a three-dimensional (3D) structure, an embedded memory device, or a solid-state hard disk. The method includes: writing at least one piece of data to at least one second physical erasing unit of at least one first physical erasing unit, and obtaining a distribution state of valid data in a plurality of physical erasing units; adjusting a specific threshold value according to the distribution state; and when the number of the at least one first physical erasing unit is less than the specific threshold value, performing a valid data merging operation.Type: GrantFiled: March 9, 2020Date of Patent: August 10, 2021Assignee: Hefei Core Storage Electronic LimitedInventor: Chong Peng
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Publication number: 20210225448Abstract: A data arranging method, a memory control circuit unit and a memory storage device for flash memory are provided. The method can be applied to a flash memory with a three-dimensional (3D) structure, an embedded memory device, or a solid-state hard disk. The method includes: writing at least one piece of data to at least one second physical erasing unit of at least one first physical erasing unit, and obtaining a distribution state of valid data in a plurality of physical erasing units; adjusting a specific threshold value according to the distribution state; and when the number of the at least one first physical erasing unit is less than the specific threshold value, performing a valid data merging operation.Type: ApplicationFiled: March 9, 2020Publication date: July 22, 2021Applicant: Hefei Core Storage Electronic LimitedInventor: Chong Peng
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Publication number: 20210223976Abstract: A data merging method for flash memory, a flash memory control circuit unit and a flash memory storage device are provided. The disclosure is applicable to a flash memory, an embedded memory device or a solid state drive of 3D structure. The method includes: selecting at least one source physical erasing unit from at least one first physical erasing unit according to a valid data count of the at least one first physical erasing unit and a valid data count of each of a plurality of memory sub-modules; and copying valid data in the at least one source physical erasing unit to at least one destination physical erasing unit to perform a valid data merging operation.Type: ApplicationFiled: March 18, 2020Publication date: July 22, 2021Applicant: Hefei Core Storage Electronic LimitedInventors: Qi-Ao Zhu, Wan-Jun Hong, Jing Zhang, Xin Wang, Xu Hui Cheng
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Publication number: 20210191635Abstract: A memory management method is provided according to the invention. The method includes: reading a physical unit and updating a read count of the physical unit; scanning the physical unit if the updated read count is not less than a read count threshold; and adjusting the read count threshold according to the read count and a read error bit. Therefore, a data unit that needs to be scanned can be determined to reduce unnecessary data scanning.Type: ApplicationFiled: February 3, 2020Publication date: June 24, 2021Applicant: Hefei Core Storage Electronic LimitedInventors: Xin Hu, Liang Xu, Xiaoyang Zhang, Zhi Wang
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Publication number: 20210181981Abstract: A memory management method. The memory management method includes: receiving a command from a host system; sending a command sequence corresponding to the command to a rewritable non-volatile memory module; determining a delay time; and sending a plurality of polling commands to the rewritable non-volatile memory module after the delay time.Type: ApplicationFiled: January 22, 2020Publication date: June 17, 2021Applicant: Hefei Core Storage Electronic LimitedInventors: Qi-Ao Zhu, Jing Zhang, Wan-Jun Hong, Ya-Lin Zhu, Tong-Jin Liu