Abstract: Embodiments described herein generally relate to the use of three-dimensional solid state memory structures, both volatile and non-volatile, utilizing a Network-on-Chip routing protocol which provide for the access of memory storage via a router. As such, data may be sent to and/or from memory storage as data packets on the chip. The Network-on-Chip routing protocol may be utilized to interconnect unlimited numbers of three-dimensional memory cell matrices, spread on a die, or multiple dies, thus allowing for reduced latencies among matrices, selective power control, unlimited memory density growth without major latency penalties, and reduced parasitic capacitance and resistance. Other benefits include a reduction in total density as compared to two-dimensional solid state memory structures utilizing a Network-on-Chip routing protocol, improved signal integrity, larger die areas, improved bandwidths and higher frequencies of operation.

Abstract: The present disclosure generally relates to spin-torque-transfer magnetoresistive random access memory (STT-MRAM) memory cells. In the magnetic tunnel junction (MTJ) of the STT-MRAM memory cell, a 1 nm thick barrier layer having a triclinic crystalline structure is doped with B, N, or C. By applying a positive voltage to the MTJ, the magnetic state of the free layer of the MTJ may be switched. By increasing the voltage applied to the MTJ, the MTJ may change to operate as a ReRAM memory cell, and the crystalline structure of the barrier layer may switch to monoclinic. Before reaching the breakdown voltage, a negative voltage may be applied to the MTJ to switch the crystalline structure of the barrier layer back to triclinic. Once the negative voltage is applied and the crystalline structure of the barrier layer is changed back to triclinic, the MTJ may function as a STT-MRAM cell once again.

Abstract: A heat-assisted magnetic recording (HAMR) disk drive has a disk with at least two independent data layers (RL1 and RL2), each data layer storing an independent data stream. At a high laser power both RL1 and RL2 are heated to above their respective Curie temperatures and a first data stream is recorded in both RL1 and RL2. At a lower laser power only upper RL2 is heated to above its Curie temperature and a second data stream is recorded only in RL2. The data layers are separated by a nonmagnetic spacer layer (SL) that prevents lower RL1 from being heated to above its Curie temperature at low laser power. The first and second data streams are typically asynchronous. Recorded data is read back from both data streams simultaneously as a composite readback signal. A joint Viterbi detector detects the asynchronous data streams simultaneously from the composite readback signal.

Abstract: A heat-assisted magnetic recording (HAMR) disk has multiple independent data layers, each data layer being a continuous non-patterned layer of magnetizable material. Each data layer can store data independent and not related to the data stored in the other data layers. The data layers are separated by a nonmagnetic spacer layer (SL) and each data layer is formed of high-anisotropy (Ku) material so that the coercivities of lower and upper data layers (RL1 and RL2) are greater than the magnetic write field. At a high laser power both RL1 and RL2 are heated to above their respective Curie temperatures and data is recorded in both RL1 and RL2. At low laser power only upper RL2 is heated to above its Curie temperature and data is recorded only in RL2. The SL prevents lower RL1 from being heated to above its Curie temperature at low laser power.

Abstract: According to one embodiment, a magnetic medium includes a substrate, and a magnetic recording layer positioned above the substrate, the magnetic recording layer including an ordered alloy having a L10-type structure, where the ordered alloy comprises a plurality of ferromagnetic crystal grains surrounded by non-magnetic grain boundaries, and where the ordered alloy comprises Fe, Ni and Pt.

Abstract: An apparatus for programming at least one multi-level Phase Change Memory (PCM) cell having a first terminal and a second terminal. A programmable control device controls the PCM cell to have a respective cell state by applying at least one current pulse to the PCM cell, the control device controlling the at least one current pulse by applying a respective first pulse to the first terminal and a respective second pulse applied to the second terminal of the PCM cell. The respective cell state is defined by a respective resistance level. The control device receives a reference resistance value defining a target resistance level for the cell, and further receives an actual resistance value of said PCM cell such that the applying the respective first pulse and said respective second pulse is based on said actual resistance value of the PCM cell and said received reference resistance value.

Abstract: A method and apparatus is provided for extending a read bandwidth and increasing a high-frequency signal-to-noise ratio (SNR) of a front-end of a read path of a hard disk drive (HDD) by introducing a high impedance section at the front-end of the read path. The high impedance section may mitigate capacitive effects found at the front-end of the read path, thereby improving signal transfer by extending the read bandwidth.

Abstract: A hermetically-sealed hard disk drive (HDD) utilizes a laminated film enclosure to hermetically seal an HDD within. The laminated film enclosure may be constructed of a heat sealant layer hermetically-sealed around the HDD, a barrier layer which inhibits gas from escaping from inside the laminated film enclosure, and a film surface protective layer which protects the heat sealant and barrier layers. Embodiments may include a heat sealant layer comprising a thermoplastic polymer such as polypropylene, a barrier layer comprising a metal such as aluminum, and a film surface protective layer comprising a thermoplastic polymer such as polyethylene terephthalate.

Abstract: Embodiments of the present disclosure generally relate to memory devices having enhanced perpendicular magnetic anisotropy. The memory device includes a plurality of first leads, a plurality of second leads, and a plurality of memory cells having a plurality of magnetic layers and a tunneling barrier layer. An interfacial layer is incorporated in each memory cell between one of the magnetic layers and the tunneling barrier layer to enhance perpendicular magnetic anisotropy, while preserving high tunneling magnetoresistance.

Abstract: The present disclosure relates to methods, apparatuses, systems, and computer program products for processing commands for accessing solid state drives. Example methods can include receiving, from a host, a loaded command availability message. The loaded command availability message can indicate that a command associated with the loaded command availability message uses a low latency mode. The methods can further include executing the associated command.

Abstract: Embodiments of the present disclosure generally relate to electronic devices, and more specifically, to multi-level phase change devices. In one embodiment, a memory cell device is provided. The memory cell device generally includes a top surface, a bottom surface and a cell body between the top surface and the bottom surface. The cell body may include a plurality of phase change material layers, which may be used to store data of the cell. In another embodiment, a method of programming a memory cell is provided. The method generally may include applying a sequence of different pulses to each phase change material layer of the cell as the voltage of each pulse in the sequence is ratcheted down from the start of a write cycle to the end of a write cycle.

Abstract: A system, according to one embodiment, includes a magnetic head having: a near field transducer, an optical waveguide for illumination of the near field transducer, and an anti-reflection block positioned along the optical waveguide farther from a media facing side of the magnetic head than the near field transducer. The anti-reflection block is positioned a distance from the near field transducer to destructively interfere with light reflected away from the near field transducer. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: Techniques for peer-to-peer Peripheral Component Interconnect Express (PCIe) storage transfers are disclosed. In some embodiments, the techniques may be realized as a method for providing peer-to-peer storage transfers between PCIe devices including providing, in memory of a first PCIe device, a queue for data communicated between the first PCIe device and a target PCIe device, receiving, at the first PCIe device, queue memory allocation information transmitted from a host device communicatively coupled to the first PCIe device and the target PCIe device, and generating, using a computer processor of the first PCIe device, a storage command.

Abstract: According to one embodiment, a magnetic recording medium includes: a substrate, a seed layer positioned above the substrate, and a magnetic recording layer structure positioned above the seed layer. The magnetic recording layer structure includes: a first magnetic recording layer having a plurality of FePtCu magnetic grains and a first segregant, and a second magnetic recording layer positioned above the first magnetic recording layer, the second magnetic recording layer having a plurality of FePt magnetic grains and a second segregant, where a Curie temperature of the first magnetic recording layer is lower than a Curie temperature of the second magnetic recording layer.

Abstract: A head gimbal assembly for a hard disk drive comprises a flexure having a planar surface and a standoff structure extending from the planar surface, where the standoff structure includes a monolithic element. A head slider in which a read-write head is housed is adhered to the flexure with an adhesive, such that the adhesive surrounds the monolithic element so that the monolithic element may absorb strain energy caused by curing of the adhesive.

Abstract: Embodiments disclosed herein generally relate to hermetic electrical connectors used in hard disk drives. The hermetic electrical connector includes a barrier structure having a first plurality of connecting pads disposed on a first surface of the barrier structure and a second plurality of connecting pads disposed on a second surface of the barrier structure opposite the first surface. A plurality of conductors is disposed within the barrier structure, and each conductor is coupled to a connecting pad of the first plurality of connecting pads and a corresponding connecting pad of the second plurality of connecting pads. The barrier structure further includes a dielectric material between the first and second surfaces, and one or more layers embedded in the dielectric material. The addition of the layers helps choke the helium gas flow, thus improving sealing of the electrical connector while maintaining high-speed electrical transmission.

Abstract: A memory cell including a floating gate transistor including a floating gate, and an analog sensor element adjacent to the floating gate, where an electrical characteristic of the analog sensor element is affected by an amount of charge on the floating gate.

Abstract: In one general embodiment, a magnetic medium includes a recording layer having at least three exchange control layers each having a magnetic moment less than 100 emu/cc, and four magnetic layers separated from one another by the exchange control layers. An uppermost of the magnetic layers is doped with oxygen. In another general embodiment, a magnetic medium includes a recording layer having at least three exchange control layers and four magnetic layers separated from one another by the exchange control layers. An uppermost of the magnetic layers has an oxygen content of greater than 0.5 vol %. An average pitch of magnetic grains in a lowermost of the magnetic layers is 9 nm or less. A lowermost of the magnetic layers has an oxide content of at least 20 vol %.

Abstract: An actuator rotational limiter mechanism for a multiple disk-stack, shared actuator hard disk drive includes an actuator comb with a cam-lock feature and an actuator limiter with a rotatable cam-roller that is engagable with the cam-lock feature to temporarily hold in place the actuator comb. The cam-lock feature may be positioned at or near a middle location of a back arm of the actuator armature, where the actuator comb being held in place by the cam-roller corresponds to the head slider being positioned on a load/unload ramp between adjacent disk stacks.

Abstract: Embodiments of the present invention include a memory unit and a processor coupled to a memory unit. The processor is operable to group a plurality of subsets of data from an input data stream and compute a first hash value corresponding to a first grouped subset of data. Additionally, the processor is operable to detect a match between the first hash value and a second hash value stored in a hash table. Furthermore, the processor is also configured to monitor a hash value match frequency for the input data stream in which the processor is operable to increment a counter value responsive to a detection of the match and determine an entropy level for the input data stream based on the counter value relative to a frequent hash value match threshold.