Patents Assigned to Hitachi Device Engineering Co., Ltd.
  • Publication number: 20140159245
    Abstract: A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another.
    Type: Application
    Filed: February 12, 2014
    Publication date: June 12, 2014
    Applicants: Renesas Electronics Corporation, Hitachi Device Engineering Co., Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Taku KANAOKA, Masashi SAHARA, Yoshio FUKAYAMA, Yutaro EBATA, Kazuhisa HIGUCHI, Koji FUJISHIMA
  • Publication number: 20140140145
    Abstract: A data input buffer is changed from an inactive to an active state after the reception of instruction for a write operation effected on a memory unit. The input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by turning on a power switch to cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, it is rendered inactive in advance before the instruction is provided, whereby wasteful power consumption is reduced. In another aspect, power consumption is reduced by changing from the active to the inactive state in a time period from a write command issuing to a next command issuing.
    Type: Application
    Filed: January 26, 2014
    Publication date: May 22, 2014
    Applicants: HITACHI DEVICE ENGINEERING CO., LTD., RENESAS ELECTRONICS CORPORATION
    Inventors: Binhaku TARUISHI, Hiroki MIYASHITA, Ken SHIBATA, Masashi HORIGUCHI
  • Publication number: 20140043348
    Abstract: A display control device and technique for controlling displays on a display unit, in which a plurality of display segments are two-dimensionally arranged (e.g. a dot matrix type display unit), is provided. The technique is effectively applicable to a write data latch circuit of a memory for storing display data in the display control device, such as, for example, a liquid crystal display control device, a mobile electronic apparatus, etc. A display drive control technique for controlling a moving picture display mode of a display device is also provided. The display drive control circuit controls a picture display mode of a display device for displaying still pictures and moving pictures to a liquid crystal display device, such as, for example, a dot matrix type display devices, an organic EL display device, etc.
    Type: Application
    Filed: September 11, 2013
    Publication date: February 13, 2014
    Applicants: Hitachi Device Engineering Co., Ltd., Renesas Electronics Corporation
    Inventors: Kunihiko Tani, Yoshikazu Yokota, Goro Sakamaki, Takashi Ohyama, Shigeru Ohta, Kei Tanabe
  • Patent number: 8644090
    Abstract: A data input buffer is changed from an inactive to an active state after the reception of instruction for a write operation effected on a memory unit. The input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by turning on a power switch to cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, it is rendered inactive in advance before the instruction is provided, whereby wasteful power consumption is reduced. In another aspect, power consumption is reduced by changing from the active to the inactive state in a time period from a write command issuing to a next command issuing.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: February 4, 2014
    Assignees: Renesas Electronics Corporation, Hitachi Device Engineering Co., Ltd.
    Inventors: Binhaku Taruishi, Hiroki Miyashita, Ken Shibata, Masashi Horiguchi
  • Patent number: 8634170
    Abstract: An integrated circuit formed on a semiconductor chip includes voltage regulators for stepping down an externally-supplied power voltage to produce an internal power voltage, and internal circuits which operate based on the internal power voltage. The voltage regulators are laid in the area of the buffers and protective elements for the input/output signals and power voltages so that the overhead area due to the on-chip provision of the voltage regulators is minimized. The internal power voltage is distributed to the internal circuits through a looped main power line, with an electrode pad for connecting an external capacitor for stabilizing the internal power voltage being provided on it, so that the internal power voltage is stabilized and the power consumption of the integrated circuit is minimized.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: January 21, 2014
    Assignees: Renesas Electronics Corporation, Hitachi Device Engineering Co., Ltd.
    Inventors: Takayasu Ito, Mitsuru Hiraki, Koichi Ashiga
  • Publication number: 20130286753
    Abstract: A data input buffer is changed from an inactive to an active state after the reception of instruction for a write operation effected on a memory unit. The input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by turning on a power switch to cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, it is rendered inactive in advance before the instruction is provided, whereby wasteful power consumption is reduced. In another aspect, power consumption is reduced by changing from the active to the inactive state in a time period from a write command issuing to a next command issuing.
    Type: Application
    Filed: June 25, 2013
    Publication date: October 31, 2013
    Applicant: HITACHI DEVICE ENGINEERING CO., LTD.
    Inventors: Binhaku TARUISHI, Hiroki MIYASHITA, Ken SHIBATA, Masashi HORIGUCHI
  • Patent number: 8264893
    Abstract: A data input buffer is changed from an inactive to an active state after the reception of instruction for a write operation effected on a memory unit. The input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by turning on a power switch to cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, it is rendered inactive in advance before the instruction is provided, whereby wasteful power consumption is reduced. In another aspect, power consumption is reduced by changing from the active to the inactive state in a time period from a write command issuing to a next command issuing.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: September 11, 2012
    Assignees: Renesas Electronics Corporation, Hitachi Device Engineering Co., Ltd.
    Inventors: Binhaku Taruishi, Hiroki Miyashita, Ken Shibata, Masashi Horiguchi
  • Patent number: 8164731
    Abstract: The present invention provides a liquid crystal display device which can obviate cutting off of a peripheral region of the liquid crystal display device which is provided with an inspection circuit and can surely perform the inspection of an image display even when the peripheral region is narrowed. On a substrate of the liquid crystal display device, a pixel region which is comprised of a plurality of gate lines and a plurality of drain lines and a peripheral region which surrounds the pixel region are formed. A turn-on inspection terminal of the liquid crystal display device are formed on the peripheral region and a semiconductor chip for driving liquid crystal is formed on the inspection terminal. The semiconductor chip is electrically insulated from the inspection terminal.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: April 24, 2012
    Assignees: Hitachi Displays , Ltd., Hitachi Device Engineering Co., Ltd
    Inventors: Hiroko Hayata, Nobuyuki Ishige, Hitoshi Komeno
  • Patent number: 8139327
    Abstract: An integrated circuit formed on a semiconductor chip includes voltage regulators for stepping down an externally-supplied power voltage to produce an internal power voltage, and internal circuits which operate based on the internal power voltage. The voltage regulators are laid in the area of the buffers and protective elements for the input/output signals and power voltages so that the overhead area due to the on-chip provision of the voltage regulators is minimized. The internal power voltage is distributed to the internal circuits through a looped main power line, with an electrode pad for connecting an external capacitor for stabilizing the internal power voltage being provided on it, so that the internal power voltage is stabilized and the power consumption of the integrated circuit is minimized.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: March 20, 2012
    Assignees: Renesas Electronics Corporation, Hitachi Device Engineering Co., Ltd.
    Inventors: Takayasu Ito, Mitsuru Hiraki, Koichi Ashiga
  • Patent number: 8031546
    Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: October 4, 2011
    Assignees: Renesas Electronics Corporation, Hitachi Device Engineering Co., Ltd.
    Inventors: Binhaku Taruishi, Hiroki Miyashita, Ken Shibata, Masashi Horiguchi
  • Patent number: 7995417
    Abstract: The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: August 9, 2011
    Assignees: Renesas Electronics Corporation, Hitachi Device Engineering Co., Ltd.
    Inventors: Takesada Akiba, Shigeld Ueda, Toshikazu Tachibana, Masashi Horiguchi
  • Patent number: 7990355
    Abstract: A semiconductor integrated circuit includes a first register, a second register, a gray scale voltage generator which outputs a plurality of gray scale voltages, a decoder which selects a gray scale voltage, and an amplifier including a first transistor, a second transistor, a third transistor, and a fourth transistor. A first terminal of the first transistor and a first terminal of the second transistors are connected to a first voltage line, a first terminal of the third transistor and a first terminal of the fourth transistor are connected to a second voltage line, a second terminal of the first transistor is connected to a second terminal of the third transistor, and a second terminal of the second transistor is connected to a second terminal of the fourth transistor.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: August 2, 2011
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Mitsuru Goto, Hiroshi Katayanagi, Yukihide Ode, Yoshiyuki Saitou, Koichi Kotera
  • Patent number: 7956976
    Abstract: The present invention provides a liquid crystal display device which can obviate cutting off of a peripheral region of the liquid crystal display device which is provided with an inspection circuit and can surely perform the inspection of an image display even when the peripheral region is narrowed. On a substrate of the liquid crystal display device, a pixel region which is comprised of a plurality of gate lines and a plurality of drain lines and a peripheral region which surrounds the pixel region are formed. A turn-on inspection terminal of the liquid crystal display device are formed on the peripheral region and a semiconductor chip for driving liquid crystal is formed on the inspection terminal. The semiconductor chip is electrically insulated from the inspection terminal.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: June 7, 2011
    Assignees: Hitachi Displays, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Hiroko Hayata, Nobuyuki Ishige, Hitoshi Komeno
  • Patent number: 7944538
    Abstract: A liquid crystal display device having a narrowed peripheral area, particularly, a liquid crystal display device in which disconnection or short-circuiting of connecting lines disposed in the peripheral area is restrained is provided. The liquid crystal display device includes a pixel area having pixel electrodes, and a peripheral area surrounding the pixel area, and a gate driver and a drain driver are disposed in the peripheral area. A plurality of gate connecting lines which connect the gate driver and a plurality of gate lines are stacked in the peripheral area.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: May 17, 2011
    Assignees: Hitachi Displays, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Nobuyuki Ishige, Hitoshi Komeno
  • Patent number: 7916261
    Abstract: The present invention provides a liquid crystal display device which can obviate cutting off of a peripheral region of the liquid crystal display device which is provided with an inspection circuit and can surely perform the inspection of an image display even when the peripheral region is narrowed. On a substrate of the liquid crystal display device, a pixel region which is comprised of a plurality of gate lines and a plurality of drain lines and a peripheral region which surrounds the pixel region are formed. A turn-on inspection terminal of the liquid crystal display device are formed on the peripheral region and a semiconductor chip for driving liquid crystal is formed on the inspection terminal. The semiconductor chip is electrically insulated from the inspection terminal.
    Type: Grant
    Filed: June 22, 2007
    Date of Patent: March 29, 2011
    Assignees: Hitachi Displays, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Hiroko Hayata, Nobuyuki Ishige, Hitoshi Komeno
  • Patent number: 7881026
    Abstract: An integrated circuit formed on a semiconductor chip includes voltage regulators for stepping down an externally-supplied power voltage to produce an internal power voltage, and internal circuits which operate based on the internal power voltage. The voltage regulators are laid in the area of the buffers and protective elements for the input/output signals and power voltages so that the overhead area due to the on-chip provision of the voltage regulators is minimized. The internal power voltage is distributed to the internal circuits through a looped main power line, with an electrode pad for connecting an external capacitor for stabilizing the internal power voltage being provided on it, so that the internal power voltage is stabilized and the power consumption of the integrated circuit is minimized.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: February 1, 2011
    Assignees: Renesas Electronics Corporation, Hitachi Device Engineering Co., Ltd.
    Inventors: Takayasu Ito, Mitsuru Hiraki, Koichi Ashiga
  • Patent number: 7868860
    Abstract: The present invention realizes proper driving circuits in a driving-circuit integral type liquid crystal display device which has an increased screen size. The liquid crystal display device includes a liquid crystal display panel and a driving circuit which supplies video signals to video signal lines formed on the liquid crystal display panel. The driving circuit is comprised of a first driving circuit which is formed in a step similar to a step for forming pixels provided to the liquid crystal display panel and a second driving circuit which is connected to the liquid crystal display panel after formation of the liquid crystal display panel. The first driving circuit is constituted of a switching circuit which is capable of distributing an output of the second driving circuit to a plurality of video signal lines.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: January 11, 2011
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Hiroshi Watanabe, Shinji Yasukawa, Hidetoshi Kida, Yoshihisa Ooishi
  • Patent number: 7830347
    Abstract: A liquid crystal display device includes drain signal lines, gate signal lines, thin film transistors, and a drain driver. The drain driver includes an amplifier circuit having a switching circuit which switches between a first state and a second state, the first state being a state where a first input terminal of the amplifier circuit is coupled to an inverting input terminal and a second input terminal is coupled to a noninverting input terminal, and the second state being a state where the first input terminal is coupled to the noninverting input terminal and the second input terminal is coupled to the inverting input terminal. The amplifier circuit supplies signal voltages to the thin film transistors via the drain signal lines which are gray scale voltages one of plus and minus offset voltages in a first frame and in a second frame.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: November 9, 2010
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd., Hitachi Ulsi Systems Co., Ltd.
    Inventors: Mitsuru Goto, Hiroshi Katayanagi, Yukihide Ode, Yoshiyuki Saitou, Koichi Kotera
  • Patent number: 7830355
    Abstract: In a liquid crystal display device having a backlight, the backlight has a first state which outputs a first amount of light and a second state which generates a second amount of light and the time for the first state and the time for the second state are controlled. Due to such a constitution, the liquid crystal display device can display clear motion picture images in spite of a simple constitution thereof. Further, the liquid crystal display device can display clear and bright motion picture images.
    Type: Grant
    Filed: October 7, 2005
    Date of Patent: November 9, 2010
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd
    Inventors: Junichi Hirakata, Kikuo Ono, Akira Shingai
  • Patent number: 7821862
    Abstract: The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: October 26, 2010
    Assignees: Renesas Electronics Corporation, Hitachi Device Engineering Co., Ltd.
    Inventors: Takesada Akiba, Shigeki Ueda, Toshikazu Tachibana, Masashi Horiguchi