Abstract: The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.

Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example; which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced.

Abstract: A liquid crystal display device includes a liquid crystal display panel having plural pixels, a lighting device having at least one light source and projecting light generated by the light source on the liquid crystal display panel, and a circuit supplying a first current during a first period and a second current smaller than the first current during a second period to the light source alternately. The circuit includes a current monitoring circuit which measures the first current and the second current, and a light control circuit which adjusts a ratio of the first period to the second period based upon a signal from the current monitoring circuit.

Abstract: A liquid crystal display device capable of improving display quality by enabling proper execution of receipt and acceptance of image signals through compensation for variation in duty ratios of clock signals as input to liquid crystal driver circuitry, is provided.

Abstract: An integrated circuit formed on a semiconductor chip includes voltage regulators for stepping down an externally-supplied power voltage to produce an internal power voltage, and internal circuits which operate based on the internal power voltage. The voltage regulators are laid in the area of the buffers and protective elements for the input/output signals and power voltages so that the overhead area due to the on-chip provision of the voltage regulators is minimized. The internal power voltage is distributed to the internal circuits through a looped main power line, with an electrode pad for connecting an external capacitor for stabilizing the internal power voltage being provided on it, so that the internal power voltage is stabilized and the power consumption of the integrated circuit is minimized.

Abstract: A liquid crystal display device which includes a first substrate, a second substrate, a liquid crystal composition sandwiched between the first substrate and the second substrate, and a plurality of pixels disposed on the first substrate. Each of the plurality of pixels is supplied with a video signal via a switching element. Each of the plurality of pixels is provided with a capacitance having two electrodes in which one is connected to a first electrode of a corresponding one of the plurality of pixels and another is supplied with a pixel-potential control signal by a pixel-potential control circuit. The pixel-potential control circuit enables selection of a first voltage level and a second voltage level.

Abstract: A display device includes a plurality of gate lines, at least one data line, and a plurality of pixels connected to the plurality of gate lines and the at least one data line. The display device is configured to perform a first step of sequentially selecting N lines of the plurality of gate lines, and sequentially outputting N times display signals to the data line, and to perform a second step of selecting Z lines of the plurality of gate lines at one time, and outputting one time a blanking signal, where N and Z are natural numbers at least equal to 2. The Z lines are separate from the N lines, and the first step and the second step are repeatedly performed.

Abstract: A display device has a driver including a level converter formed of polysilicon MISTFTs. The level converter includes first, second and third N-channel MISTFTs (NMISTFTS) and first, second and third P-channel MISTFTs (PMISTFTS). Gate and first terminals of the first NMISTFT and PMISTFT, and a gate terminal of the third PMISTFT are coupled to an input terminal via a capacitance. Second terminals of the second NMISTFT and PMISTFT, and a gate terminal of third NMISTFT are coupled to the input terminal via a capacitance. A first terminal of the third PMISTFT, and second terminals of the first NMISTFT and PMISTFT are coupled to a high voltage. A second terminal of the third NMISTFT, gate and first terminals of the second NMISTFT and PMISTFT are coupled to a low voltage. A second terminal of the third PMISTFT and a first terminal of the third NMISTFT are connected to an output terminal.

Abstract: A liquid crystal display device has a liquid crystal display panel and a drive circuit for supplying gray scale voltages to pixels in the liquid crystal display panel. The drive circuit selects intended gray scale voltage levels from a gray scale voltage varying with time periodically by determining a timing corresponding to the intended voltage level of the gray scale voltage based upon a display data signal and time control signals supplied to the drive circuit. A stabilizer circuit is provided to a gray scale voltage line for supplying the gray scale voltage.

Abstract: A liquid crystal display device includes a pair of substrates which face each other with a liquid crystal layer therebetween, a plurality of gate signal lines and a plurality of drain signal lines, and a plurality of pixel regions which are formed on one substrate. A planar counter electrode which is formed on each pixel region, and a pixel electrode having a plurality of slits is formed in overlapping relation with the counter electrode. A first contact hole is provided for connecting the pixel electrode and a source electrode, and a connection line is provided for connecting the counter electrode of one pixel region and the counter electrode of an adjacent next pixel region. The counter electrode has a notch in the position of the first contact hole.

Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example; which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced.

Abstract: A liquid crystal display device with both functions of transmission-mode display and reflection-mode display is capable of providing an improved display quality in each display mode, to thereby obtain on-screen display images of high quality in either one of the display modes. The liquid crystal display device includes a scan signal line drive circuit operable to apply a scan signal to a number of scan signal lines, an image/video signal line drive circuit which applies an image signal to a number of image signal lines, and a power supply circuit for supplying necessary voltages to the scan signal line drive circuit and image signal line drive circuit. The power supply circuit includes a counter electrode voltage generation circuit for selecting a voltage optimized for a respective display mode of the transmission mode and the reflection mode to thereby apply the selected voltage to a counter electrode.

Abstract: A liquid crystal display includes pixels each having an switching element, drain drivers and gate drivers for operating the switching elements and the pixels, and drain lines and gate lines supplying signals from the drain drivers and the gate drivers to the switching elements being formed on one of a pair of substrates sandwiching a liquid crystal layer. Wiring lines are formed on the one of a pair of substrates for transferring display data signals and a clock signal to the gate drivers.

Abstract: A display device includes a substrate having plural signal lines connected to switching elements which are formed in an image display region, and plural terminals connected to respective ones of the signal lines. The terminals include a first group arranged at an image display region side and a second group arranged remote from the image display region side, the terminals being connected to output terminals of a driving circuit. The output terminals include a first group arranged at the image display region side and a second group arranged remote from the image display region side. The first group of terminals connect the first group of output terminals, and the second group of terminals connect the second group of output terminals. An area of a respective output terminal of the second group is larger than an area of a respective output terminal of the first group.

Abstract: Disclosed herewith is a semiconductor data processing device that realizes low power consumption at the standby time and at the operation time, as well as speeds up the interfacing operation. The semiconductor data processing device can connect a non-volatile storage device to a general-purpose bus of a host system. The data processing device enters the active or standby state in response to the state of the general-purpose bus. In the standby state, the data processing device stops the internal clock signal and applies a substrate bias voltage to each object so as to suppress the potential sub-threshold leak current therefrom. This bias voltage is also applied to the central processing unit and the rewritable non-volatile memory for storing a control program to be executed by the central processing unit. The central processing unit processes data in units of n bits or below when the interface controller and the data transfer controller input/output parallel data in units of 2n bits.

Abstract: An integrated circuit formed on a semiconductor chip includes voltage regulators for stepping down an externally-supplied power voltage to produce an internal power voltage, and internal circuits which operate based on the internal power voltage. The voltage regulators are laid in the area of the buffers and protective elements for the input/output signals and power voltages so that the overhead area due to the on-chip provision of the voltage regulators is minimized. The internal power voltage is distributed to the internal circuits through a looped main power line, with an electrode pad for connecting an external capacitor for stabilizing the internal power voltage being provided on it, so that the internal power voltage is stabilized and the power consumption of the integrated circuit is minimized.

Abstract: A liquid crystal display device having a liquid crystal display element having a plurality of pixels. The video signal line driver circuit includes a plurality of amplifiers each of which has a pair of a first input terminal and a second input terminal, and a plurality of pairs of an inverting input terminal and a noninverting input terminal. Each of the plurality of amplifiers has a switching circuit which switches between a first state and a second state, based on a switching control signal supplied with a switching repetition period equal to double a display line repetition period.

Abstract: A display device includes a pixel driver circuit. Each of level converter circuits in the pixel driver circuit has: an input terminal supplied with a signal swinging between a first voltage and a second voltage lower than the first voltage; a first first-conductivity-type transistor having a gate electrode coupled to the input terminal, and a source region coupled to ground; a second second-conductivity-type transistor having a gate electrode coupled to a drain region of the first transistor, a source region coupled to a power supply, and a drain region coupled to an output terminal; one circuit element among a diode, a resistor and a fourth second-conductivity-type transistor, coupled between the gate electrode of the second transistor and the power supply; a third first-conductivity-type transistor having a source region coupled to the input terminal, a drain region coupled to the output terminal, and a gate electrode supplied with a dc voltage.

Abstract: A display device includes a dynamic ratio less shift register which is operated in a stable manner and can expand the degree of freedom of design. In the dynamic ratio less shift register which is provided with thin film transistors having semiconductor layers made of p-Si on a substrate surface, a node which becomes the floating state is connected to a fixed potential through a capacitance element.

Abstract: Rupture of distance holding members, aback substrate or a front substrate attributed to atmospheric pressure is suppressed in a display device in which, between the back substrate having cathode lines and plate-member control electrodes and the front substrate, a large number of distance holding members, which maintain distance between the substrates, are mounted in an erect manner. At portions where the distance holding members are brought into contact with the back substrate and/or the front substrate, a buffering/fixing material, which is constituted of a buffering material having high resiliency and an adhesive, is interposed for dispersing the atmospheric pressure applied from the back substrate and the front substrate substantially uniformly. Further, the distance holding members are fixed between the back substrate and the front substrate by a heat treatment and a pressurizing step.