Patents Assigned to Hitachi Engineering Co., Ltd.
  • Patent number: 7814223
    Abstract: A transmit packet generated by a CPU 1 is held in a buffer 100a (100b). From among packets received from Ethernet 820a (820b), a packet, a destination of which is a communication device 800, is held in the buffer 100a (100b). A packet which should be transmitted is transmitted from a transfer judging circuit 200 to Ethernet 820a or 820b through a MAC unit 300a or 300b. If a transfer judging circuit 200 judges a packet from the Ethernet 820a to be a packet, a destination of which is another communication device, with reference to a destination MAC address, this packet is transferred to the Ethernet 820b through MAC 300b. If a usage rate of a transferring FIFO buffer 130a (130b) exceeds a threshold value in the process of transmitting a packet held in a transmitting FIFO buffer 120a (130b) on a priority basis, the priority order of a transfer packet is made higher than that of a transmit packet so that the transfer packet is transferred to the Ethernet 820a or 820b in preference to the transmit packet.
    Type: Grant
    Filed: January 29, 2008
    Date of Patent: October 12, 2010
    Assignees: Renesas Technology Corporation, Hitachi Engineering Co., Ltd., Hitachi Information & Control Systems, Inc.
    Inventors: Hiroshi Arita, Yasuhiro Nakatsuka, Yasuwo Watanabe, Kei Ouchi, Yoshihiro Tanaka, Toshinobu Kanai, Masanobu Tanaka, Kenji Furuhashi, Tomoaki Aoki
  • Patent number: 7641867
    Abstract: An exhaust gas containing a perfluoride component (PFC) and SiIF4 is conducted into a silicon remover and brought into contact with water. A reaction water supplied from a water supplying piping and air supplied from an air supplying piping are mixed with the exhaust gas exhausted from the silicon remover. The exhaust gas containing water, air, and CF4 is heated at 700° C. by a heater. The exhaust gas containing PFC is conducted to a catalyst layer filled with an alumina group catalyst. The PFC is decomposed to HF and CO2 at a high temperature exhausted from the catalyst layer is cooled in a cooling apparatus. Subsequently, the exhaust gas is conducted to an acidic gas removing apparatus to remove HF. In this way, the silicon component is removed from the exhaust gas before introducing the exhaust gas into the catalyst layer. Therefore, the surface of the catalyst can be utilized effectively, and the decomposition reaction of the perfluoride compound can be improved.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: January 5, 2010
    Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd., Hitachi Kyowa Engineering Co., Ltd.
    Inventors: Kazuyoshi Irie, Toshihiro Mori, Hisao Yokoyama, Takayuki Tomiyama, Toshihide Takano, Shin Tamata, Shuichi Kanno
  • Patent number: 7577485
    Abstract: The invention is intended to provide a building sequence planning system for an automobile production line, which can prepare an efficient building sequence. The system comprises an input unit (1) for inputting information of vehicles to be manufactured, a processing unit (3) for deciding an optimum building sequence based on the vehicle information inputted through the input unit (1), and an output unit (5) for externally outputting a building sequence schedule decided by the processing unit (3). The processing unit (3) prepares a vehicle building sequence, determines a degree of dissatisfaction of the prepared building sequence, as a penalty value, in accordance with restriction conditions which are inputted through the input unit (1) and are imposed when building the vehicles into work, and decides a building sequence with a minimum penalty by preparing a plurality of building sequences and determining the penalty value for each building sequence with respect to the restriction conditions.
    Type: Grant
    Filed: February 27, 2003
    Date of Patent: August 18, 2009
    Assignees: Hitachi, Ltd., Nissan Motor Co., Ltd., Hitachi Engineering Co., Ltd.
    Inventors: Hitoshi Onizawa, Masanori Sato, Kei Nakamura, Atsumi Ichikawa, Hiroshi Soejima, Shinichi Sakagami, Yutaka Sanada
  • Patent number: 7386067
    Abstract: A demodulating semiconductor integrated circuit device used in a wireless communication system of an FM-modulation scheme, wherein a circuit for canceling a frequency offset is made of a digital circuit, so as to make a high-accuracy decision as to received data and prevent error frequency offset cancel due to a pseudo pattern contained in the received data. Consequently, a high-accuracy received data decision is carried out.
    Type: Grant
    Filed: October 13, 2006
    Date of Patent: June 10, 2008
    Assignees: Renesas Technology Corporation, Hitachi Engineering Co., Ltd.
    Inventors: Takao Kobayashi, Masaaki Shida, Kazuhiko Kawai
  • Patent number: 7382681
    Abstract: A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: June 3, 2008
    Assignees: Renesas Technology Corp., Hitachi Engineering Co., Ltd.
    Inventors: Naoki Yada, Yasuyuki Saito, Yasushi Shibatsuka, Katsunori Koike, Mitsuhiko Okutsu
  • Patent number: 7367192
    Abstract: In a combined cycle plant that combines a conventional thermal power plant and a gas turbine plant, there is provided a dump system 1 that connects a main steam pipe 60 with the condenser 25 and dumps the steam generated by the boiler 10 into the condenser 25, bypassing the steam turbine; and HRSG HP turbine bypass system 2 and HRSG LP turbine bypass system 3 which connect the HP pipe 70 and LP pipe 71 of the heat recovery steam generator, respectively.
    Type: Grant
    Filed: May 5, 2005
    Date of Patent: May 6, 2008
    Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.
    Inventors: Youichi Hattori, Taiji Inui
  • Patent number: 7310717
    Abstract: A data processor including a central processing unit and a data transfer control unit is disclosed. The data transfer control unit has an address register for storing a transfer address. The data transfer control unit transfers data according to a transfer unit size selected from a plurality of transfer unit sizes. If the address register contains an odd address as an initial value, the data transfer control unit transfers data according to a different transfer unit size that is smaller than the selected transfer unit size. If the data transfer control unit determines that a remaining quantity of data to be transferred is smaller than the selected transfer unit size, the selected transfer unit size is switched to a smaller transfer unit size selected from the plurality of transfer unit sizes.
    Type: Grant
    Filed: June 4, 2003
    Date of Patent: December 18, 2007
    Assignees: Renesas Technology Corp., Renesas Northern Japan Semiconductor, Inc., Hitachi Engineering Co., Ltd.
    Inventors: Tatsuo Nishino, Toru Ichien, Gou Teshima, Hiromichi Ishikura, Jyunji Ishikawa
  • Patent number: 7307421
    Abstract: An MRI apparatus having a configuration that reduces vibration of a static magnetic field generating source is provided. A closed vessel 2 of the static magnetic field generating source is provided with a rigid structure 4 for preventing transmission of vibration generated from a gradient magnetic field generating part 21 to other members via the closed vessel 2. The rigid structure 4 uses, for example, a connecting part 4 that connects a face 25 on the imaging space side and a face 26 confronting it. The rigidity of the closed vessel is thereby increased, and therefore vibration transmitted from the gradient magnetic field generating part can be reduced. The connecting part can have a through-hole structure, and in such a case, internal space of through-hole can be used for drawing cables.
    Type: Grant
    Filed: April 22, 2004
    Date of Patent: December 11, 2007
    Assignees: Hitachi Medical Corporation, Hitachi Ltd., Hitachi Engineering Co., Ltd.
    Inventors: Akira Kurome, Kenji Sakakibara, Hirotaka Takeshima, Takeshi Yatsuo, Hiroyuki Watanabe, Yoshihide Wadayama, Hirofumi Motoshiromizu, Kunihito Suzuki
  • Patent number: 7287430
    Abstract: A method of connecting hollow conductors with a brazing alloy employs a measuring mechanism 10 for measuring a connecting state of a connecting portion after brazing hollow conductors. The measuring mechanism comprises a scanner 101 and a holder 19, which are separated in advance, so that the mechanism can be installed in a narrow space. A display mechanism 20 displays measuring results as tow-dimensional patterns, and the evaluation mechanism 30 evaluate the connecting portions by an area of the defects and an integral length of sound portions. A judgment mechanism 40 evaluates relative relation of the measuring results with causes-and-defects, which are previously stored, and shows the cause of the defect.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: October 30, 2007
    Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.
    Inventors: Masami Sukeda, Yasuaki Kageyama, Norihiro Watanabe, Shinya Odajima, Hideo Tanahashi, Masahiro Koike, Yoshinori Musha, Kazutoshi Ikeda
  • Patent number: 7276908
    Abstract: In the MRI apparatus of the present invention, a reinforcing member is firmly provided so as to enhance the rigidity strength of two connecting tubes connecting upper and lower cryostats, thereby suppression of vibration caused by a gradient magnetic field coil and suppression of variation of static magnetic field can be realized. Further, in the MRI apparatus of the present invention, the reinforcing member is provided in upper and lower portions of the connecting tubes of the vacuum vessels, thereby suppression of vibration caused by the gradient magnetic field coil and suppression of variation of static magnetic field can be realized. Further, in the MRI apparatus of the present invention, the reinforcing member is provided in upper and lower parts of the vacuum vessels, thereby suppression of vibration caused by the gradient magnetic field coil and suppression of variation of static magnetic field can be realized.
    Type: Grant
    Filed: June 23, 2005
    Date of Patent: October 2, 2007
    Assignees: Hitachi, Ltd., Hitachi Medical Corporation, Hitachi Engineering Co., Ltd.
    Inventors: Kunihito Suzuki, Hirofumi Motoshiromizu, Kunihiro Takayama, Yoshihide Wadayama, Akira Kurome, Shin Hoshino
  • Patent number: 7196967
    Abstract: A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: March 27, 2007
    Assignees: Renesas Technology Corp., Hitachi Engineering Co., Ltd.
    Inventors: Naoki Yada, Yasuyuki Saito, Yasushi Shibatsuka, Katsunori Koike, Mitsuhiko Okutsu
  • Patent number: 7193929
    Abstract: A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: March 20, 2007
    Assignees: Renesas Technology Corp., Hitachi Engineering Co., Ltd.
    Inventors: Naoki Yada, Yasuyuki Saito, Yasushi Shibatsuka, Katsunori Koike, Mitsuhiko Okutsu
  • Patent number: 7141221
    Abstract: An exhaust gas containing a perfluoride component (PFC) and SiF4 is conducted into a silicon remover and brought into contact with water. A reaction water supplied from a water supplying piping and air supplied from an air supplying piping are mixed with the exhaust gas exhausted from the silicon remover. The exhaust gas containing water, air, and CF4 is heated at 700° C. by a heater. The exhaust gas containing PFC is conducted to a catalyst layer filled with an alumina group catalyst. The PFC is decomposed to HF and CO2 at a high temperature exhausted from the catalyst layer is cooled in a cooling apparatus. Subsequently, the exhaust gas is conducted to an acidic gas removing apparatus to remove HF. In this way, the silicon component is removed from the exhaust gas before introducing the exhaust gas into the catalyst layer. Therefore, the surface of the catalyst can be utilized effectively, and the decomposition reaction of the perfluoride compound can be improved.
    Type: Grant
    Filed: May 16, 2001
    Date of Patent: November 28, 2006
    Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd., Hitachi Kyowa Engineering Co., Ltd.
    Inventors: Kazuyoshi Irie, Toshihiro Mori, Hisao Yokoyama, Takayuki Tomiyama, Toshihide Takano, Shin Tamata, Shuichi Kanno
  • Patent number: 7142213
    Abstract: In a device and system which perform processing (displaying and outputting) of image data, the amount of data transferred between a memory holding the image data and a processor processing the image data is limited, thereby a great amount of data can be processed at high speed.
    Type: Grant
    Filed: April 13, 2004
    Date of Patent: November 28, 2006
    Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.
    Inventors: Yasuhiro Nakatsuka, Keisuke Nakashima, Shigeru Matsuo, Masahisa Narita, Koyo Katsura, Hidehito Takewa, Tomoaki Aoki
  • Patent number: 7136433
    Abstract: A demodulating semiconductor integrated circuit device used in a wireless communication system of an FM-modulation scheme, wherein a circuit for canceling a frequency offset is made of a digital circuit, so as to make a high-accuracy decision as to received data and prevent error frequency offset cancel due to a pseudo pattern contained in the received data. Consequently, a high-accuracy received data decision is carried out.
    Type: Grant
    Filed: July 23, 2002
    Date of Patent: November 14, 2006
    Assignees: Renesas Technology Corp., Hitachi Engineering Co., Ltd.
    Inventors: Takao Kobayashi, Masaaki Shida, Kazuhiko Kawai
  • Patent number: 7126448
    Abstract: An MRI apparatus includes magnet members for compensating the magnetic field which are disposed to a thermal shield system of the superconducting apparatus. The magnet members for compensating the magnetic field are disposed at positions where temperature change in the vacuum chamber is not transferred to the interior of the vacuum chamber.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: October 24, 2006
    Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.
    Inventors: Hiroyuki Watanabe, Masanori Takahashi, Mitsushi Abe, Jun Kawamura
  • Patent number: 7061825
    Abstract: A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: June 13, 2006
    Assignees: Renesas Technology Corp., Hitachi Engineering Co., Ltd.
    Inventors: Naoki Yada, Yasuyuki Saito, Yasushi Shibatsuka, Katsunori Koike, Mitsuhiko Okutsu
  • Patent number: 6983585
    Abstract: In a combined cycle plant that combines a conventional thermal power plant and a gas turbine plant, there is provided a dump system 1 that connects a main steam pipe 60 with the condenser 25 and dumps the steam generated by the boiler 10 into the condenser 25, bypassing the steam turbine; and HRSG HP turbine bypass system 2 and HRSG LP turbine bypass system 3 which connect the HP pipe 70 and LP pipe 71 of the heat recovery steam generator, respectively.
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: January 10, 2006
    Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.
    Inventors: Youichi Hattori, Taiji Inui
  • Patent number: 6982060
    Abstract: An object of the present invention is to provide a chemical decontamination liquid decomposing system having a catalyst tower which has a mesh filter capable of certainly preventing catalyst from flowing out and a mechanism of pushing-down the catalyst capable of preventing convection of the catalyst caused by decomposition gas. The catalyst tower in accordance with the present invention used for decomposing a chemical decontamination liquid comprises an inlet pipe, a catalyst for decomposing the chemical decontamination liquid, an outlet mesh filter for preventing the catalyst from flowing out, an outlet pipe, a catalyst charging port for charging the catalyst, a catalyst pushing-down mechanism for preventing occurrence of convection of the catalyst caused by a decomposed gas and so on. The outlet mesh filter is arranged so as to closely attached to the inner surface of the catalyst tower and to the inner surface of the catalyst charging port.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: January 3, 2006
    Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.
    Inventors: Motoaki Sakashita, Katsuo Yokota, Yasushi Kobayashi, Kazumi Anazawa
  • Patent number: 6937339
    Abstract: In an inspection device for inspecting for possible foreign matters contaminating a liquid filled transparent container, a red color illumination unit 23A is disposed behind a glass container 22 filled with liquid and a pair of blue color illumination units 23B and 23C are disposed so as to sandwich the red color illumination unit 23A. Both the red color and blue color illumination units 23A, 23B and 23C are disposed so that the red color light transmits through the glass container 22 and the blue color light reflected by a possible foreign matter in the liquid merges with the red color transmission light. Both the transmission light and the reflection light are separated by a color separation mirror 4 and are imaged by CCD cameras 5 and 6 so as to detect both black color series and white color series foreign matters can be detected at the same time.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: August 30, 2005
    Assignee: Hitachi Engineering Co., Ltd.
    Inventors: Hiromi Yamazaki, Tadahiro Katane, Hirohisa Fukuda, Kunitaka Asano, Mitsuhiro Matsushima