Abstract: The object of the present invention is to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of breakthrough current, despite entry of the input signal featuring low-amplitude operations, and said integrated circuit device comprising a gate circuit, memory and processor.

Abstract: A system for automatically dividing the form of an object to be analyzed using a finite element method, etc., into meshes, includes initial group generation means for generating a plurality of area division forms based on the form of the analysis object input through input means, and area division form evaluation means the generated area division forms. If the evaluation result does not satisfy a predetermined determination criterion, end determination means starts selection and crossover means for generating a new group and further starts mutation means for deforming the area division forms of the new group, then again starts the area division form evaluation means. If the evaluation result satisfies the predetermined determination criterion, an optimum area division form in the group is adopted as the optimum area division form. Division-into-meshes means subdivides the optimum area division form into meshes. The result of subdividing into the meshes is output to mesh output means.

Abstract: A graphic data generating apparatus includes a data processor, a graphic memory, and a graphic processor. The data processor outputs instructions to the graphic processor for processing graphic data. The instructions include a drawing instruction for transferring graphic data stored in a predetermined location in the graphic memory to another predetermined location in the graphic memory. The graphic memory stores pixel data defining the graphic data and each of the pixel data having a plurality of bits. The graphic processor performing read out of word data having a plurality of pixel data at a word position of the graphic memory specified by a source memory address, selecting pixel data specified by a source pixel address in the readout word and writing the selected pixel data in the graphic memory at a pixel position specified by a destination pixel address of word data specified by the destination memory address.

Abstract: A system for making an optimum plan for a given problem at high speed. The system sets a planning problem, etc., prepares an objective function and finalizes a plan for minimizing or maximizing the objective function value, and then stores necessary variables. The system prepares as many parent plans of a first generation as a given number (population), calculates objective function values, sorts plans in descending or ascending order of the objective function values of the plans, when selection numbers are assigned to plans in order of a ratio of the objective function value of each plan to the total of the objective function values of the plans, selects parent plans by using numbers indicated by as many constants as the population determined for each generation as the selection numbers, and replaces two elements, arranged at order positions specified by random numbers, with each other for each of the selected parent plans, to prepare child plans.

Abstract: A graphic pattern processing apparatus having a display memory, a data processor, a graphic processor, and a plurality of parallel to serial convertors. The display memory stores graphic data in words, each word has a plurality of pixel data and each pixel data has a plurality of bits. A graphic processor accesses the display memory and processes a plurality of the pixel data in response to instructions received from a data processor. The number of parallel to serial convertors corresponds to the number of bits per pixel and are configured to allow a word from the display memory to be converted into a serial stream of pixel data.

Abstract: A graphic pattern processing apparatus having a graphic memory, a data processor, and a graphic processor. The graphic memory stores a pattern composed of pixel data. The graphics processor includes a plurality of color registers. The graphic processor reads the graphic memory in response to instructions received from the data processor. The graphics processor in response to the pixel data read from the graphic memory selects one of a plurality of color registers and outputs that value.

Abstract: A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.

Abstract: A graphic pattern processing apparatus for accessing a memory which stores words of graphic data. A plurality of pixels is stored in each word and each pixel has a plurality of bits. Each pixel of the word may be selected by a pixel address supplied by a graphic data processor. The graphic data processor performs processing on the selected pixel in accordance with instructions received from a data processor.

Abstract: A planning system for quickly forming the optimum plan for a given planning problem, includes a setting unit for accepting the given planning problem; an optimization unit for creating an objective function which expresses an item intended to be minimized or maximized in the planning problem, and for executing a process which minimizes or maximizes a value of the created objective function; a storage unit for storing therein, at least, constant values which are required for the optimizing process; and a display unit for displaying a processed result of the optimization unit.

Abstract: A reactor core coolant flow rate control system for a BWR type nuclear power plant in which electric power is generated by a turbine-driven generator driven by a steam turbine rotating under the work of a main steam generated from a cooling water recirculated through a boiling water reactor includes an internal pump driving unit comprised of an electric motor driven by an electric power generated by the turbine-driven generator, a fluid coupling for transmitting an output torque of the electric motor and a variable-frequency generator whose rotation number is changed in accordance with the torque transmitted by way of the fluid coupling, a fluid coupling control signal generating unit for generating a fluid coupling control signal for the fluid coupling in response to at least one of deviation in a load and a rotation speed of the turbine-driven generator and deviation in a rotation speed of the internal pumps, and a plurality of internal pumps for recirculating the cooling water.

Abstract: A communication line driver for a communication interface includes on one chip, a trimming circuit for adjusting a reference voltage generated by a reference voltage generating circuit, a driving device for transmitting a signal to a communication line; a buffer for applying a constant voltage to the driving device by a constant voltage control based on an output of the trimming circuit, and a bias circuit for deciding an internal operating current of the buffer on the basis of the output of the trimming circuit. The buffer further includes an MOS transistor which operates as a current limiter and functions to limit the current in case of an overload. Thus, a resistor for the current control is unnecessary. An electric power consumption can be reduced by the current limitation at the time of overload.

Abstract: The interface portion of a coprocessor is provided with a FIFO (First-In First-Out) buffer and means for accepting instructions in succession. Pipeline control of the instructions becomes possible in this way, and protocol means associated with a microprocessor is also provided.

Abstract: A fuel assembly comprises a plurality of fuel rods, tie plates for holding both ends of these fuel rods, and spacers which support these fuel rods. The spacer comprises a plurality of cells into which the fuel rods are inserted respectively, the adjacent cells being joined to each other at axial ends thereof, whereby a space between these cells being held or retained, and a plurality of loop springs held respectively on the cells. Each of the loop springs has a pair of resilient members which are located within the pair of adjacent cells and which urge the fuel rods in a radial direction, and a pair of connections which connect axial ends of the resilient members to each other. Each of the connections have a passage through which coolant flows axially and which is defined by a closed peripheral wall. The closed peripheral wall is not uniform in thickness. The pair of adjacent cells have at axial end portions of peripheral walls openings for accommodating or receiving the connections of the loop spring.

Abstract: A high-speed image signal processing system for encoding an image signal, read out at a high speed, into an encoded signal, and/or for recording a decoded signal obtained through a decoding operation on an encoded signal. The image signal, obtained through a scanning operation on an original document, is sent to an encoder through an image bus. A code bus, provided at an output of the encoder, is connected with an encoded-signal memory for storing the encoded signal. A code transfer unit, for performing input/output operation over the encoded signal and for performing transfer of the encoded signal from the code bus to a system bus, is disposed between the code bus and the system bus. A control unit, performing control over the entire system, and a document management data memory, storing management data for performing management over documents stored in the encoded-signal memory, are connected to the system bus.

Abstract: A graphic processor which controls reading, writing and transfer of graphic data for a display memory that stores graphic data. The processor includes a first unit which stores first address information for addressing the display memory and first pixel address information which points a pixel position in a word specified by the first address information, a second unit which stores second address information for addressing the display memory and second pixel address information which points a pixel position in a word specified by the second address information, a third unit which shifts graphic data of multiple pixels included in two consecutive words to extract continuous 1-word graphic data, and a fourth unit which implements drawing computations pixel-wise concurrently for one word depending on the number of pixels included in a word.

Abstract: A neural network system includes a qualitative evaluation section, a neural network section, a quantifying section and a display section. The qualitative evaluation section qualitatively analyzes an unknown data supplied thereto, and normalizes the result of analysis within a predetermined range. The neural network section having a neural network with plural neurons computes the network output data from the normalized unknown data produced by the qualitative evaluation section. Each neuron is connected to plural other neurons through synapses, each of which is assigned an individual weight coefficient. Each neuron is adapted to output an output function value assigned thereto associated with the total sum of the products of the output from the neurons connected thereto and the synapse weight coefficient. The quantifying section quantifies the network output data to produce desired data. The desired data thus produced is displayed on the display section.

Abstract: A superconductive apparatus having therein at least a superconductive member includes a lithium containing member so as to interrupt neutrons directed to the superconductive member.

Abstract: A method and apparatus for displaying on a display screen the controlling circuit in a plant controlling system for controlling a plant by a controller using a microcomputer. The display screen is segmented into a software region and a hardware region. The software circuit which is realized by software is displayed in the software region, and the hardware circuit related to the software circuit is displayed in the hardware region. The information, which is plotted during the interactive process and is displayed in the software regions, is automatically translated into a program for controlling the controller. Operation data of the plant is also given on the display screen. Desired circuit elements of the software circuit may be selected to change parameters of the circuit elements. Maintenance work can be carried out while observing the indication on the display screen without any aid of documents such as the maintenance manual or the like.

Abstract: A data transmitting/receiving apparatus comprises a master clock signal and a slave clock signal which differ in phase with each other according to a basic clock signal. Serial data is input according to the produced master clock signal or slave clock signal, a protocol process is applied to the input serial data, and the serial data subjected to the protocol process is output according to the master clock signal or the slave clock signal. A start delimiter detecting signal is generated when a start delimiter indicating the first frame is detected in the input serial data and phases are exchanged between the master clock signal and the slave clock signal when there arises a shift on a bit boundary of the serial data when the start delimiter detecting signal is generated.

Abstract: There is disclosed a coil structure which can be rapidly energized or excited, and which reduces the generation of heat in a coil container by an eddy current due to a dynamic disturbance such as vibration and a magnetic field fluctuation, thereby suppressing the occurrence a quench. The coil container is constituted by a low-resistivity material, and a high-resistivity portion is provided at at least one portion of the coil container in the direction of the periphery of the coil container. The high-resistivity portion is provided at a position where a vibration displacement is small or a magnetic field fluctuation is small. When the coil structure is to be energized or excited, the eddy current produced in the direction of the periphery of the superconducting-coil container can be reduced at the high-resistivity portion, and when the dynamic disturbance develops, the generation of heat by the eddy current is suppressed by the low-resistivity material.