Abstract: YA semiconductor memory is provided with memory cells for storing a plurality of sets of data, each of the sets having check bits. A selecting circuit selects some of the memory cells to form a set in response to a first address signal. The circuit includes an error correcting code circuit, a tristate circuit and a control circuit which forms a control signal to control the tristate circuit. Output terminals of the tristate circuit are coupled with external output terminals of the semiconductor memory. Also, the tristate circuit is controlled by the control signal to bring the external circuit terminals into high impedance at least during the time when the error correcting code circuit is delivering indefinite data.

Abstract: The address of each defective memory cell in a memory cell array is stored within a semiconductor ROM in advance. In parallel with the operation of reading out information from a memory cell of the array, whether or not the address of the memory cell agrees with the previously stored address of a defective memory cell is distinguished. When they agree, a correcting signal is formed. Erroneous data read out from the defective memory cell is inverted on the basis of the correcting signal and thus corrected, whereupon the corrected data is delivered out of the ROM. In using this error data correcting system, a read-out access time delay caused by furnishing the correcting function corresponds to only one stage of a logic circuit which is used for the inversion to correct the erroneous data. Thus, a semiconductor ROM furnished with an error correcting function can be provided without spoiling enhancement in the speed of the read-out operation.

Abstract: An integrator circuit comprising reset means by which, when it is detected that an integrator output V.sub.p for an input analog signal coincides with a plus or minus reference value, the integral output is reset to the vicinity of the middle of the plus and minus reference values, in effect, without interrupting the integrating operation; a circuit which produces a pulse each time coincidence is detected; and a circuit which produces a direction signal indicating whether the coincidence results from an increase or a decrease of the integral input.The pulses produced in the state in which the direction signal is indicating an increase are counted up, and the pulses produced in the state in which the direction signal is indicating a decrease are counted down, whereby the precise integral value of the input analog signal can be detected.

Abstract: An address multiplex type system for a dynamic RAM includes a memory cell array having a plurality of memory cells which are simultaneously selected by signals output from an address decoder, a decoder, and a shift register. The dynamic RAM further includes a selecting circuit which receives a plurality of address signals applied externally through one of a plurality of pins of a package in a time-sharing manner and makes it possible to write or read data into or from one memory cell of the plurality of memory cells selected. The dynamic RAM can read out or write in serially data of a plurality of memory cells selected from the memory cell array when a shift register operates. The dynamic RAM can also read or write data serially into or from a plurality of memory cells selected from the memory cell array simply by connecting the pin to a predetermined potential.

Abstract: In a dynamic RAM having a memory array of a folded bit line arrangement, the memory array has a plurality of bit line pairs. A plurality of word lines and dummy word lines cross each of the bit line pairs so as to apply coupling noises of the same phase to the bit lines constituting each of the bit line pairs. The levels of the coupling noises applied to the bit lines constituting each of the bit line pairs, however, are also affected by the stray capacitance between the bit lines. Since the bit line disposed at an end part of the memory array has only one adjacent bit line disposed on one side thereof, only a relatively small stray capacitance is connected to the bit line. This causes the coupling noise between bit lines at the bit line disposed at an end part of the memory array to be different than the degree of coupling noise between other bit lines in the array.

Abstract: In a magnetic bubble memory device in which magnetic bubbles are propagated under influence of a rotating magnetic field, a method of controlling a stop operation of a rotating magnetic field in which magnetic field is caused to further rotate beyond the stop direction for a predetermined over-rotation angle and is then caused to return to the stop direction which is followed by the removal of the magnetic field, is presented. The over-rotation angle is in a range of 10 to 40 degrees. The invention is applicable whether bubble drive is performed using a drive current of triangular, square or trapezoidal waveform.

Abstract: A semiconductor device has a diffused layer of a first conductivity type which extends to a buried layer of a second conductivity type, formed in a manner to extend from a part of a surface of a semiconductor layer of the second conductivity type which is epitaxially grown on a semiconductor substrate of the first conductivity type through the buried layer of the second conductivity type. A semiconductor junction capacitance is formed of the diffused layer of the first conductivity type and the buried layer of the second conductivity type, and the concentration of an impurity to be introduced into the buried layer of the second conductivity type is controlled.

Abstract: A time constant circuit capable of switching the characteristic, which is realized by a combination of an equivalent resistor made up of a switched capacitor and an ordinary capacitor, comprises a capacitor of the switched capacitor or the time constant circuit connected in parallel to a series circuit including a switching device and an additional capacitor. The characteristic is switched by turning on and off the additional capacitor by the switching device. The direct connection of a plurality of equivalent resistors with a plurality of switched capacitors and ordinary capacitors makes up an equalizer. The capacitor making up a switched capacitor is connected with a switching device and an additional capacitor so that the frequency characteristic of the equalizer is switchable by turning on and off the switching device. Each of the capacitors making up the switched capacitors, the capacitors making up the time constant circuits and the additional capacitors has an end thereof grounded.

Abstract: An abnormal surge voltage such as frictional static electricity is often applied to the external terminals of a MOSIC. In the past, the output MOS transistor in the MOSIC during normal handling of the device frequently will have its gate insulating film broken down by the application of such an abnormal surge voltage to the drain thereof. In order to prevent the gate insulating film from being broken down, in this manner a resistor is connected between the gate of the output MOS transistor and a drive circuit for driving that output MOS transistor. This construction using a resistor is superior to the construction in which the voltage to be applied to the drain of the output MOS transistor is clamped by the use of suitable clamp means only because, with the resistor arrangement, the output characteristics of the MOSIC are not restricted.

Abstract: In a static type RAM, a sense amplifier includes first and second dissymmetric type differential amplifier circuits each of which has a pair of differential transistors and an active load circuit such as a current mirror circuit connected to the drains of the differential transistors. One of balanced signals delivered from a memory cell is supplied to the non-inverting input terminal of the first dissymmetric type differential amplifier circuit and the inverting input terminal of the second dissymmetric type differential amplifier circuit. The other of said balanced signals is applied to the remaining input terminals of the first and second dissymmetric type differential amplifier circuits. As a result, notwithstanding that balanced signals cannot be delivered from each dissymmetric type differential amplifier circuit, amplified balanced signals can be obtained.

Abstract: In a MOS static RAM, data lines disposed in a memory array and common data lines to be coupled with the data lines through a data line selection circuit are supplied with bias voltages of a level lower than a power source voltage level through bias MOSFETs. Normally, where the stand-by period of the RAM is long, the bias voltages of the data lines and the common data lines are abnormally raised by the leakage currents or tailing currents of the bias MOSFETs. As a result, the data read-out speed of the RAM is lowered. Such abnormal potential increases of the data lines and the common data lines are prevented by connecting resistance elements of comparatively high resistances (such as made of polycrystalline silicon layers), between the respective data lines and common data lines and the ground point of the circuitry.

Abstract: A semiconductor device has a diffused layer of a first conductivity type which extends to a buried layer of a second conductivity type, formed in a manner to extend from a part of a surface of a semiconductor layer of the second conductivity type which is epitaxially grown on a semiconductor substrate of the first conductivity type through the buried layer of the second conductivity type. A semiconductor junction capacitance is formed of the diffused layer of the first conductivity type and the buried layer of the second conductivity type, and the concentration of an impurity to be introduced into the buried layer of the second conductivity type is controlled.

Abstract: A motor driving circuit in which the opposite ends of the motor driving coils of a video tape recorder (VTR) capstan motor are shorted by a group of switching elements when a control input voltage generated from a rotation detection/oscillator is in a predetermined range.

Abstract: A signal voltage dividing circuit in which two switched capacitors each including an input terminal, an output terminal and a capacitor connected selectively to the input terminal or the output terminal are connected in series and driven in opposite phase with each other. A holding capacitor is connected between the junction of the two switched capacitors and a reference potential. An input signal is supplied across the two switched capacitors to produce a divided output signal from the junction of the two switched capacitors.

Abstract: In the past, it has been a problem in integrated circuits using MOSFETs that the gate insulating film of a transmission gate MOSFET is broken down when an abnormally high voltage such as is caused by frictional static electricity is applied to its drain region. This breakdown of the gate insulating film cannot be prevented merely by limiting the voltage level applied to the drain region to a level below the breakdown withstand voltage of the gate insulating film. The reason for this is that even with such voltage limiting, the breakdown of the gate insulating film can still occur when local heating is generated by a relatively large breakdown current flowing through the drain junction. To prevent such a breakdown of the gate insulating film, therefore, a resistance element for limiting the breakdown current is connected in series with the drain region of the transmission gate MOSFET.

Abstract: An output of a noise canceller which cancels a noise component from within a composite video signal is applied to an input of an AGC detector which generates an AGC voltage for controlling the gain of a video intermediate frequency amplifier. A circuit controlled by a pulse provided from a vertical oscillator, thereby to control the noise cancelling operation of the noise canceller associated with the operation of the AGC detector into an inoperative state in a vertical flyback time is arranged, so that the lockout phenomenon under various receiving conditions of the television receiver can be prevented.

Abstract: This invention is directed to a punch-through reference diode comprising a first semiconductor region of a first conductivity type which is formed within a semiconductor body; a second semiconductor region of a second conductivity type which is formed within the semiconductor body, the second semiconductor region adjoining the first semiconductor region and defining a first PN-junction with the first semiconductor region; and a third semiconductor region of the first conductivity type which is formed within the semiconductor body, the third semiconductor region adjoining the second semiconductor region and defining a second PN-junction with the second semiconductor region, whereby the second semiconductor region is located between the first PN-junction and the second PN-junction.

Abstract: A converter includes a voltage selector which employs IGFETs as voltage switching elements, and a controller which controls the IGFETs. Each of the IGFETs in the voltage selector is made either the P-channel type or the N-channel type, depending upon a voltage level to be thereby switched and a level of a binary signal supplied from the controller. As a result, a voltage of comparatively great level can be switched by a binary signal of small level amplitude.

Abstract: The phase detection circuit includes a first phase detector for receiving an input signal and a first reference signal, a second phase detector for receiving the input signal and a second reference signal having a different phase from that of the first reference signal and a level discriminator for receiving the phase detection output of the first phase detector. The detection operation of the second phase detector can be inhibited directly by means of the discrimination output of this level discriminator. Accordingly, the phase detection output can be obtained from this phase detection circuit only when the phase difference between the input signal and the first reference signal falls within a predetermined range. The phase detection circuit having such a limiting function is suitable for application to an automatic tint control circuit of a color television receiver.

Abstract: A chroma signal gain control circuit is constructed to include a first band pass amplifier, a second band pass amplifier, a burst gate circuit, a switch circuit and an ACC detecting circuit. The output signal of the first band pass amplifier is fed to the input of the second band pass amplifier, the output signal of which is fed to the input of the burst gate circuit. The switch circuit selectively transmits either the output of the burst gate circuit or the output of the second band pass amplifier to the ACC detecting circuit. The gain of the first band pass amplifier is controlled by feeding the detected output of the ACC detecting circuit to the first band pass amplifier. In order to prevent over-saturation in case the level ratio (C/B) between the color burst signal and the chroma signal exceeds a predetermined value, the switch circuit will selectively transmit the output of the second band pass amplifier to the ACC detecting circuit.