Abstract: A logic design automation system examines correspondence relationship among sublogics in intermediate gate-level logic (containing neither physical design information nor manually optimized logic design information) produced from updated functional-level logic and current gate-level logic (containing the above information) to identify corresponding sublogics and non-corresponding sublogics of the gate-level logics with reference to primary input/output signals and input/output gates. For the corresponding sublogics, the corresponding sublogics of the current gate-level logic are selected, and for the non-corresponding sublogics, the non-corresponding sublogics of the intermediate gate-level logic are selected. The selected sublogics are combined to synthesize updated gate-level logic which preserved therein the physical design information and the manually optimized logic design information for portions of the current gate-level logic which need not be modified.

Abstract: A semiconductor integrated circuit device includes a semiconductor nonvolatile memory, a booster circuit which generates a high voltage required for writing the data into said semiconductor nonvolatile memory, and a control circuit. With the thus constructed device, however, various external control signals often fail to assume definite levels when the power source is closed. If an operation mode to be designated is erroneously determined to be a write operation mode due to obscure levels of the external control signals, then the write operation is executed erroneously. To prevent such an eronneous operation from developing when the power source is closed, provision is made of a power souce closure detector circuit and a suitable gate circuit. Owing to these circuits, the output of the booster circuit is prevented from being applied to the memory element from the time from when the power source circuit is closed up to the time when the read operation mode is designated by an external control signal.

Abstract: An MOS static type RAM has a memory cell array comprising of a plurality of static type memory cells arranged in matrix, a plurality of data lines connected to the data input-output terminals of the respective memory cells and a plurality of word lines connected to the selection terminals of the respective memory cells. Data line load circuits are disposed between the power terminal of the circuit and the data lines. Each data line load circuit is kept at a relatively high impedance in the data write-in operation, and at a relatively low impedance in the data read-out operation. The use of the data line load circuits comprised of such variable impedance circuits can speed up the operating speed of the RAM and can accomplish lower power consumption.

Abstract: Herein disclosed is a semiconductor device including a plurality of IIL elements which are electrically connected by a plurality of first wirings arranged generally parallel with one another and a plurality of second wirings arranged generally parallel with one another and extended in different direction to the first wirings.

Abstract: A data converting system converts CRT display data into display data for another display unit such as a liquid crystal display unit by use of a memory. The system includes a data load controller which selects one segment of data out of two segments of data in the CRT display data successively while changing the segment position to be selected alternately in every two frame scanning periods so that the CRT display data for one complete picture is written into the memory in two frame scanning periods, i.e., a segment is written into the memory once for every two adjacent segments. Display data is read out of the memory in the data form conformable to the other display unit.

Abstract: A semiconductor memory includes a dummy cell for forming a reference potential, a read-only memory cell, and a differential amplifier circuit which receives the reference potential formed by the dummy cell and a signal read out from the memory cell. The differential amplifier circuit is dynamically operated so that the semiconductor memory is made smaller in power consumption and size than conventional units. Moreover, in order to reduce the power consumption, the memory cell is brought into the nonselection state when a predetermined time has passed after being selected. In addition, the semiconductor memory is provided with a compensating circuit in order to make the value of the capacitance connected to a word line for transmitting a selecting signal to the memory cell and the value of the capacitance connected to a dummy word line for transmitting a selecting signal to the dummy cell substantially equal to each other.

Abstract: An information processing apparatus for executing instructions in parallel includes circuitry which, when a first instruction requesting reading of an operand from a certain address of the main storage or buffer storage has been decoded, detects among instructions in execution the presence of a second instruction requesting writing of an operand held by a register such as a general-purpose register into that address of the main storage without implementing an operation on the operand. If the second instruction has been detected, the invention reads out an operand from the register specified for operand reading by said second instruction before operand writing into the main storage by the second instruction is completed.

Abstract: Disclosed are memory cells of a vertical-type read only memory (ROM) having a plurality of MISFETs connected in series. The MISFETs include gate electrodes formed with multiple conductive layers, in which some of the MISFETs are set to the depletion type and at least some of the remaining MISFETs are set to the enhancement type, so as to write information in the memory cells. The information write operation is conducted through at least two steps. Namely, in the first information write step, gate electrodes are used as a mask to implant an impurity; and in the second step, an impurity is implanted through the gate electrodes into the surface of the semiconductor substrate. These steps enable a semiconductor memory device, such as a vertical-type mask ROM having memory cells with a reduced series resistance and being suitable for a high degree of integration, to be produced.

Abstract: In an analysis processor which utilizes a parameter table for setting a processing condition and analyzes data in accordance with the content of table, a process for registering/correcting the parameter table is standarized for various analysis processing programs so that each of the analysis processing programs is divided into an analysis processing procedure instruction section and a parameter table section. Thus, a plurality of different analysis process can be performed in one analysis processor. Any table in the analysis processing programs may be readily referred to by an instruction through a keyboard of the analysis processor and may be registered and corrected. Thus, a user can alter the analysis processing program as he/she desires.

Abstract: A resistor is provided with a plurality of turn parts whose corners have an obtuse flexional angle in order to improve the relative resistance precision. A ladder resistor can be formed with a plurality of such resistors connected in series, and various electronic devices are formed employing the ladder resistor.

Abstract: In a resin packaged semiconductor device including a semiconductor element, the back side of which is bonded to a support and the front side of which has electrodes which are electrically connected to electroconductive portions by fine leads, when an adhesive composition comprising an epoxy resin, a novolak type phenolic resin, a solvent for the both resins and a powdery filler, and if necessary, a curing accelerator and a coupling agent, is used for binding the semiconductor and the support, the resulting semiconductor device is excellent in moisture resistance and corrosion resistance.

Abstract: In a buffer memory, a validity flag to be added to each data portion is stored in a tag array or address section at a location corresponding to each data portion. After determining whether each validity flag is to be used as a search object, based upon the data portion to be accessed during searching the tag array and an access mode, the address and its validity flag are simultaneously searched. The logical sum of each output of the search result on a word coincidence line becomes a hit judgement signal.

Abstract: Herein disclosed is a process of fabricating a semiconductor integrated circuit device, in which there is formed between a conductive layer prepared by covering a polycrystalline silicon layer with either a layer containing a refractory metal of high melting point, i.e., a refractory metal layer or a silicide layer of the refractory metal and a first insulating film made of phosphosilicate glass flowing over said conductive layer containing the refractory metal, a second insulating film preventing the layer containing a refractory metal from peeling from the polycrystalline silicon layer by the glass flow. The second insulating film is formed by deposition to have a thickness not smaller than a predetermined value.

Abstract: An MOS static type RAM has a memory cell array comprising a plurality of static type memory cells arranged in matrix, a plurality of data lines connected to the data input-output terminals of the respective memory cells and a plurality of word lines connected to the selection terminals of the respective memory cells. Data line load circuits are disposed between the power terminal of the circuit and the data lines. Each data line load circuit is kept at a relatively high impedance in the data write-in operation, and at a relatively low impedance in the data read-out operation. The use of the data line load circuits comprised of such variable impedance circuits can speed up the operating speed of the RAM and can accomplish lower power consumption.

Abstract: A buffer or a plurality of buffers are provided each for holding a write address and an address specifying a write position which are obtained as a result of an execution based on a predicted result. The execution of the instruction is continued up to the operation stage regadless of whether or not the instruction is being executed in the predicted state, the data and the write address are held in the buffer written. The data in the buffer is canceled if the prediction is found to be wrong when the predicted state is completed, and the data is utilized if the prediction is found to be correct.

Abstract: In a network system wherein a plurality of terminal devices communicates with each other via respective node devices over a ring transmission line, a transmitting node device can confirm whether a multicast information transmission has succeeded or failed. The transmitting node device send a response frame after a multicast information frame. A receiving node device relays the multicast information frame and a response frame from the upstream node device to the downstream one when the multicast information has been received successfully, or in case of a failure in receiving the multicast information, sends a response frame to the downstream node device by changing at least part of the response frame from the upstream node device. The transmitting node device can determine from a received response frame if there is one or more of the receiving node devices which cannot receive the multicast information.

Abstract: Herein disclosed is a DRAM which has such a carrier trapping region around a memory cell array as can trap minority carriers deep in a semiconductor substrate so that the minority carriers to be generated in the semiconductor substrate by alpha rays may be sufficiently trapped. The memory cell of the DRAM has a capacitor which is partially formed of the semiconductor substrate. The carrier trapping region is formed by making use of trenches or a well region.

Abstract: A still picture reproducing system for a magnetic recording and reproducing apparatus is disclosed. The system sends one frame in order to shift a reproduction mode from ordinary reproduction to reproduction of a still picture by use of so-called "fine slow", sends one more frame if a noise is detected on a picture at this time, and stops if no noise is detected.

Abstract: A semiconductor memory includes a word line driving circuit whose output terminal is coupled to one end of each word line of a memory array, and also an auxiliary driving circuit which drives the other end of the word line upon receiving a selection signal transmitted to the other end of this word line. The auxiliary driving circuit comprises a level detector circuit which is dynamically driven by a timing signal, and a driving element which is driven by an output of the level detector circuit to drive the other end of the word line. When the word line is to be reset, the output of the level detector circuit is set at a level which brings the driving element into an "off" state. The auxiliary driving circuit of this arrangement permits the other end of the word line to change to a selection level quickly and to be reset quickly.

Abstract: In a multilayer circuit board wherein a plurality of electronic parts are provided on a first principal plane, a plurality of brazing pads for pins are respectively arranged on a second principal plane and a plurality of wiring layers having wiring nets for connecting said electrical parts are formed between these principal planes. The EC pads for I/O leads for connecting discrete wires is provided to said first principal plane. EC pads are provided on said second principal plane and are connected to the brazing pads for pins in such a manner as to be electrically separable as required. The EC pads for I/O leads and the brazing pads for pins are connected through the interior of the multilayer circuit board and the EC pads are connected to the wiring net through the interior of the multilayer circuit board.