Abstract: A graphic drawing method and system are provided to display a composite graphic composed of a plurality of fundamental graphics wherein an operator designates at least two points on a display screen using a pointing device to automatically display a straight line or a curve coupling the two points. As the coordinates input mode, there are provided an ordinary input mode and an auto-adjust mode. If a coordinate input command is given in the auto-adjust mode, it is determined whether the coordinates already inputted are present within a small area spaced apart by a predetermined distance from the cursor position. If present in the small, predetermined area, the coordinates already inputted are used as the present input coordinates. If not present in the small, predetermined area, the position coordinates of the cursor are used as the input coordinates.

Abstract: A semiconductor memory device having a plurality of memory arrays in which static memory cells are disposed in a lattice arrangement at intersections of word lines and complementary data lines. The load circuits thereof are characterized as having a varying impedance effected by the combination of a first pair of P-channel MOSFETs disposed between the complementary data lines and a first node supplied with a first supply voltage and kept normally in an ON-state, and a pair of transistors, such as a second pair of P-channel MOSFETs, similarly connected as the first pair of P-channel MOSFETs and which are turned off selectively in accordance with a control signal corresponding to a predetermined selection timing signal in a write-in mode. The semiconductor memory device has a plurality of switching circuits which are coupled between the plurality of complementary data lines and a pair of data read and write lines.

Abstract: When data are memorized in a 2-7 RLL code on a disc shaped memorizing medium using a sector format, as an address mark in each sector a 2-7 illegal pattern is used; a 1-byte data "8B" in an NRZ signal is converted into a 2-7 RLL code, and further it is modified into the 2-7 illegal pattern.A disc controller in a disc memory inserts the 1-byte data "8B" into a specified position in an NRZ signal and transmits it to an encoder/decoder. In the encoder, the 1-byte data "8B" in an NRZ signal is detected, and a 2-7 illegal pattern is formed by reversing a specified bit of a 2-7 RLL code formed by converting the 1-byte data "8B", and the illegal pattern is sent to the read/write amplifier.

Abstract: With the reduction in the size of semiconductor integrated circuit devices, there have been increases in the resistance at the contact portions of metal interconnections and in the incidence of contact failure. To solve these problems, the present invention provides a novel interconnection structure.

Abstract: A micro computer has a free-running counter, a first capture register served with counted data from the free-running counter, and a second capture register which is selectively served with the data held in the first capture register or the counted data from the free-running counter. The second capture register works as a save register for the first capture register. This makes it possible to increase the precision of the timer unit in the micro computer, enabling the timer unit to find general applicability more extensively.

Abstract: A monolithic semiconductor integrated circuit device includes a differentially operative circuit section, an amplifying element connected to define a current flowing in the differentially operative circuit section and a circuit for adjusting a current flowing in the amplifying element to thereby compensate for variations of electric characteristics from one semiconductor device to another. The current adjusting circuit includes at least one amplifying element and a load resistance for the amplifying element in the current adjusting circuit. The load resistance has a structure suitable for a trimming operation to adjustably determine the resistance value of the load resistance.

Abstract: In a scheduling system, constraints changing based on situations and scheduling know-how are implemented according to the knowledge engineering method, whereas computations for the concrete, optimal allocation are conducted according to the mathematical programming method. As a result, there can be achieved a scheduling which can easily cope with changes in the scheduling know-how and constraints and which has a high maintainability and a high computation speed.

Abstract: In a semiconductor integrated circuit device, such as a ROM having an instruction program set therein, in which an order for selecting word lines is variously different depending upon written information; a method of manufacture which can shorten a production process after the determination of the instruction program or the circuit arrangement of a decoder without adding to a manufacturing step is disclosed.

Abstract: A method of designing semiconductor integrated circuits wherein rough routes are designated after a process of design for cells layout is completed, then wirings between cells are supposed automatically on the basis of the designated rough routes, investigation of the characteristic of the wirings is executed, and after a target characteristic is attained, a wiring pattern satisfying all of required electrical and physical conditions, including layout rules, i.e. a detailed wiring pattern, is prepared.

Abstract: The present invention is characterized in that, in a ball wedge bonding using a fine bonding wire precoated with a thin insulating layer, ultrasonic vibration is applied to a capillary to effect the delivery of the wire smoothly during movement of the capillary to a second bonding point while delivering the wire after ball bonding at a first bonding point.

Abstract: Disclosed is a semiconductor integrated circuit wherein a logic circuit for exchanging signals with RAMS, with the RAMS being disposed centrally on the semiconductor chip or substrate, is divided into a plurality of logic circuits in accordance with the kind of signals and the divided logic circuits are disposed around the RAM in such a manner as to minimize the distance of signal transmission paths with the RAM and in order to attain high speed access to RAMS.

Abstract: An image reconstruction method for a magnetic resonance imaging device is disclosed, by which phase distortions of a magnetic resonance signal are stored in the form of a table prepared previously, by using a phase encode amount and an imaging region size as parameters; the phase distortions of the magnetic resonance signal are corrected on the basis of the phase distortions stored in the table for the measured magnetic resonance signal or the phase distortions varying for every line are presumed from the difference in the phase between the phase of hypothetical data including no phase distortions and the phase of measured data; and the phase distortions of the measured magnetic resonance signal are corrected by using this presumed value.

Abstract: An electronic system having a first and a second semiconductor device acting as a microprocessor and a coprocessor, respectively, disposed linearly on a mounting board. The external pins common to both the first and the second semiconductor device are connected by wiring means installed linearly on the mounting board.

Abstract: In a semiconductor integrated circuit device having memory cell arrays, power source wirings are provided on the memory cell array in parallel with the long side of the memory cell array, thereby strengthening the power source wirings without increasing a chip size and planning reduction in power source impedances.

Abstract: A single-chip microcomputer has external terminals outputting a system clock signal, an address signal, and a data signals. External equipment such as an external memory is operated by address and signal which are output when the system clock signal changes. In the single-chip microcomputer of this invention, the operation of an address signal output circuit and that of a data signal output circuit are controlled by a signal output from a digital delay circuit which receives the system clock signal. According to this circuit construction, the hold time between the change in the system clock and the change in the address and data signals is determined by the delay circuit which exhibits a digital operation, so that the hold time can be set accurately without being affected adversely by any variation in the circuit elements due to the manufacturing process, or by temperature changes.

Abstract: A data name standardizing/unifying system for standardizing the names of data belonging to data items having different names and transferred or compared among data files so as to be unified for programs. For standardizing the data names, names of data items assumed to have same contents are gathered and a table indicating data names to be replaced are generated to be displayed together with prompting for entry of the standard data name to replace. From this table, standardization for data names is accomplished by this replacement of the data name in the programs. For identifying the standardized data names created for the different files, different file names or different and upper file names are added to a division of program which refers to the files.

Abstract: An external sync signal generated by a clock generation circuit inside a single-chip microcomputer is supplied to an external terminal of this chip. The external sync signal is necessary in an external expansion mode but not in a single-chip mode. Therefore, the external sync signal is supplied to the external terminal through a control gate while a suitable control signal is inputted to a control terminal of the control gate. According to this circuit construction, control can be made in such a manner that the external sync signal is not supplied to the output terminal in the single-chip mode. As a result, it becomes possible to prevent noise from entering a signal supplied to an adjacent pin through a coupling capacity between the external terminals in the single-chip mode, and to reduce consumed power of an output buffer circuit which is disposed between the control gate and the external terminals.

Abstract: A semiconductor memory device is provided which includes a plurality of memory arrays each including main word lines, sub word lines to which a plurality of memory cells are connected, and a decoder which selectively connects the sub word lines to the main word lines. The main word lines are relatively short, since they are isolated electrically between memory arrays, and their resistance can thus be relatively low. The main word lines are not directly connected with a plurality of memory cells, and this results in a smaller capacitance coupled to the main word lines than is customarily the case. Consequently, the semiconductor memory device can have an enhanced operating speed.

Abstract: A method is provided for manufacturing a master slice semiconductor integrated circuit device. Initially, a first total circuit diagram which is to be reformed into a master slice semiconductor integrated circuit device is defined. First and second circuit points on the first total circuit block which are to be used respectively as input and output terminals of the master slice semiconductor integrated circuit device are specified. Next, signal transmitting paths are successively traced from the output to the input of each logic gate located in the signal transmitting paths in actual use. In the course of the tracing, these traced gates are marked and the logic gates actually in use are identified. As a result, in addition to those logic gates having unused output terminals, the gates constituting a closed loop isolated from the signal transmitting paths for transmitting substantial output signals are identified as unnecessary gates and deleted.

Abstract: In a data processing system having a central processing unit, at least an input/output unit such as an MT unit or a floppy disk unit, a memory, an address bus, a first address translation unit, a second address translation unit, and an address selection unit, an output address from the central processing unit is translated by the first address translation unit to supply a resultant address to the address bus and, an output address from the input/output unit is directly fed to the address bus. An address on the address bus is delivered to the address selection unit, and the address selection unit selectively supplies the memory with the output address delivered from the first translation unit onto the address bus or with the resultant address obtained by translating the output address from the input/output unit by means of the second translation unit.