Patents Assigned to Hitachi Tohbu Semiconductor, Ltd
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Patent number: 8455986Abstract: A semiconductor device featuring a semiconductor chip having a first main surface and a second, opposing main surface and including a MOSFET having source and gate electrodes formed on the first main surface and a drain electrode thereof formed on the second main surface, first and second conductive members acting as lead terminals for the source and gate electrodes, respectively, are disposed over the first main surface, each of the first and second conductive members has a part overlapped with the chip in a plan view, a sealing body sealing the chip and parts of the first and second conductive members such that a part of the first conductive member is projected outwardly from a first side surface of the sealing body and parts of the first and second conductive members are projected outwardly from the opposing second side surface of the sealing body in a plan view.Type: GrantFiled: April 30, 2012Date of Patent: June 4, 2013Assignees: Renesas Electronics Corporation, Hitachi Tohbu Semiconductor, Ltd.Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
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Patent number: 8183607Abstract: A semiconductor device features a semiconductor chip including a MOSFET, a first electrode of the MOSFET disposed on an obverse surface of the chip, a second, control electrode of the MOSFET disposed on the obverse surface, a third electrode of the MOSFET disposed on a second, opposing surface of the chip, first, second, and third conductive members, each having top surface and opposing bottom surface, the first, second, and third conductive members connecting with the first, second, and third electrodes electrically, respectively, a sealing body having top and bottom surfaces and sealing parts of the first, second, and third conductive members, the first conductive member having first, second, and third contiguous portions, the first portion is positioned over the first electrode, the second is positioned between the first and second portions and the third portion is positioned under the obverse surface of the chip.Type: GrantFiled: July 25, 2011Date of Patent: May 22, 2012Assignees: Renesas Electronics Corporation, Hitachi Tohbu Semiconductor, Ltd.Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
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Patent number: 7985991Abstract: A semiconductor device features a semiconductor substrate with a MOSFET, an electrode for main current of the MOSFET disposed on a first major surface of the substrate, an electrode for control of the MOSFET disposed on the first major surface, a rear plane electrode of the MOSFET disposed on a second, opposing surface of the substrate, and an external connection terminal electrically connected to the rear plane electrode, the external electrode contains a first part, a second part and a third part, the first part is positioned over the rear plane electrode, the third part is positioned below the second major surface and the third part is connected via the second part to the first part.Type: GrantFiled: March 12, 2008Date of Patent: July 26, 2011Assignees: Renesas Electronics Corporation, Hitachi Tohbu Semiconductor, Ltd.Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
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Patent number: 7525813Abstract: In a semiconductor device such as a high-frequency power amplifier module, a plurality of amplifying means are formed on a semiconductor chip which is mounted on a main surface of a wiring substrate, and electrodes of the semiconductor chip are electrically connected by wires to electrodes of the wiring substrate. In order to make the high-frequency power amplifier module small in size, a substrate-side bonding electrode electrically connected to a wire set at a fixed reference electric potential is place at a location farther from a side of the semiconductor chip than a substrate-side output electrode electrically connected to an output wire. A substrate-side input electrode electrically connected to an input wire is located at a distance from the side of the semiconductor chip about equal to the distance from the side of the semiconductor chip to the substrate-side output electrode, or at a location farther from the side of the semiconductor chip than the substrate-side bonding electrode is.Type: GrantFiled: October 1, 2007Date of Patent: April 28, 2009Assignees: Renesas Technology Corp., Hitachi Tohbu Semiconductor, Ltd.Inventors: Iwamichi Kohjiro, Yasuhiro Nunogawa, Sakae Kikuchi, Shizuo Kondo, Tetsuaki Adachi, Osamu Kagaya, Kenji Sekine, Eiichi Hase, Kiichi Yamashita
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Patent number: 7400002Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.Type: GrantFiled: October 31, 2006Date of Patent: July 15, 2008Assignees: Renesas Technology Corp., Hitachi Tohbu Semiconductor, Ltd.Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
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Patent number: 7394146Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.Type: GrantFiled: October 31, 2006Date of Patent: July 1, 2008Assignees: Renesas Tehcnology Corp., Hitachi Tohbu Semiconductor, Ltd.Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
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Patent number: 7351946Abstract: An AD-converted digital video data is encoded by a difference encoding method before it is outputted and such encoded digital video data is then outputted, after it is converted to gray code or to a predetermined code in which a fixed value is added. Problems solved include noise that is generated when the AD conversion circuit outputs video data and that migrates into a CCD side via a power supply line on a printed circuit board, and noise that appears on a display image by migration into an input terminal side from an output circuit side via the power supply line and a semiconductor substrate within an AD conversion LSI.Type: GrantFiled: December 1, 2004Date of Patent: April 1, 2008Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Hitachi Tohbu Semiconductor, Ltd.Inventors: Yasutoshi Aibara, Hiroki Nakajima, Eiki Imaizumi, Tatsuji Matsuura
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Patent number: 7342267Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.Type: GrantFiled: May 2, 2006Date of Patent: March 11, 2008Assignees: Renesas Technology Corp., Hitachi Tohbu Semiconductor, Ltd.Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
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Patent number: 7332757Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.Type: GrantFiled: May 2, 2006Date of Patent: February 19, 2008Assignees: Renesas Technology Corp., Hitachi Tohbu Semiconductor, Ltd.Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
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Patent number: 7278577Abstract: An image input system includes a solid state image pickup device and a preprocessor for performing correlated double sampling amplification on an output of the image pickup device and outputting a video signal. The preprocessor has a correlated double sampling amplifier for outputting signal information corresponding to a difference voltage between the black level in a feedthrough period of the image pickup device and a signal level in a charge signal output period; and an offset cancelling circuit for cancelling an offset voltage corresponding to the difference voltage in a state where the image pickup device is optically interrupted to the input terminal of the correlated double sampling amplifier. The correlated double sampling amplifier cancels out the offset voltage and the offset cancelling voltage as signal components of polarities opposite to each other, so that circuits following the correlated double sampling amplifier are not influenced by the offset voltage.Type: GrantFiled: April 14, 2004Date of Patent: October 9, 2007Assignees: Renesas Technology Corp., Hitachi Tohbu Semiconductor, Ltd.Inventors: Kouichi Yahagi, Masumi Kasahara, Hiroki Nakajima
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Patent number: 7145394Abstract: A high frequency power amplifier module of a multistage amplifier construction comprising: an input terminal; an output terminal; a control terminal; and a mode switching terminal. The first amplification stage includes a dual gate FET, and a bias voltage according to a signal is applied to the first gate and the second gate of the dual gate FET from the control terminal and the mode switching terminal, and a radio signal from the input terminal is applied to the second gate such as the source of the dual gate FET. In dependence upon the signal from the mode switching terminal, the mode of the high frequency power amplifier module is for the GSM (i.e., for a non-linear amplifying action) and for the EDGE (for a linear amplifying action).Type: GrantFiled: April 5, 2005Date of Patent: December 5, 2006Assignees: Renesas Technology Corp., Hitachi Tohbu Semiconductor, Ltd.Inventors: Masahito Numanami, Hitoshi Akamine, Tsuyoshi Shibuya, Tetsuaki Adachi, Masatoshi Morikawa, Yasuhiro Nunogawa
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Patent number: 7122775Abstract: An AD-converted digital video data is encoded by a difference encoding method before it is outputted and such encoded digital video data is then outputted, after it is converted to gray code or to a predetermined code in which a fixed value is added. Problems solved include noise that is generated when the AD conversion circuit outputs video data and that migrates into a CCD side via a power supply line on a printed circuit board, and noise that appears on a display image by migration into an input terminal side from an output circuit side via the power supply line and a semiconductor substrate within an AD conversion LSI.Type: GrantFiled: April 5, 2004Date of Patent: October 17, 2006Assignees: Renesas Technology Corp., Hitachi ULSI System Co., Ltd., Hitachi Tohbu Semiconductor, Ltd.Inventors: Yasutoshi Aibara, Hiroki Nakajima, Eiki Imaizumi, Tatsuji Matsuura
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Patent number: 7084055Abstract: It is desirable to prevent breakage and separation of wiring of a semiconductor integrated circuit device, such as a bit-line of a DRAM. To accomplish this, disclosed is a method in which, e.g., a high density plasma silicon oxide film is deposited on wirings (e.g., a bit-line that is connected to the source and drain region of a memory cell selection MISFET of a DRAM memory cell) by means of a high density plasma CVD technique, at a first temperature, and the structure is subjected to RTA (heat treatment) at a second temperature higher than the first temperature (e.g., 750° C.). Via holes are then formed in the high density plasma silicon oxide film, and first and second conductive films are then formed, the first conductive film being formed in the via holes and at a third temperature lower than the first temperature. The first and second conductive layers are then polished to remain selectively within the via holes.Type: GrantFiled: September 1, 2004Date of Patent: August 1, 2006Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd., Hitachi Tohbu Semiconductor, Ltd.Inventors: Tsuyoshi Fujiwara, Katsuyuki Asaka, Yasuhiro Nariyoshi, Yoshinori Hoshino, Kazutoshi Oomori
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Patent number: 7068521Abstract: In a semiconductor device such as a high-frequency power amplifier module, a plurality of amplifying means are formed on a semiconductor chip which is mounted on a main surface of a wiring substrate, and electrodes of the semiconductor chip are electrically connected by wires to electrodes of the wiring substrate. In order to make the high-frequency power amplifier module small in size, a substrate-side bonding electrode electrically connected to a wire set at a fixed reference electric potential is place at a location farther from a side of the semiconductor chip than a substrate-side output electrode electrically connected to an output wire. A substrate-side input electrode electrically connected to an input wire is located at a distance from the side of the semiconductor chip about equal to the distance from the side of the semiconductor chip to the substrate-side output electrode, or at a location farther from the side of the semiconductor chip than the substrate-side bonding electrode is.Type: GrantFiled: August 2, 2005Date of Patent: June 27, 2006Assignees: Renesas Technology Corp., Hitachi Tohbu Semiconductor, Ltd.Inventors: Iwamichi Kohjiro, Yasuhiro Nunogawa, Sakae Kikuchi, Shizuo Kondo, Tetsuaki Adachi, Osamu Kagaya, Kenji Sekine, Eiichi Hase, Kiichi Yamashita
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Register capable of corresponding to wide frequency band and signal generating method using the same
Patent number: 6986072Abstract: A maximum value of the number of mounted memory devices is assumed, and a value of an external delay replica is fixed and set. A desired frequency band is divided into a plurality of sub-frequency bands, and delay times of an output buffer and an internal delay replica are switched and used every sub-frequency band, thereby setting an actual maximum value and an actual minimum value to the internal delay replica. A selecting pin can select the delay time in the internal delay replica. Thus, it is possible to sufficiently ensure a set-up time and a hold time of an internal clock signal generated by a delay locked loop circuit in the latch operation in a register within a desired frequency band and with a permittable number of memory devices, irrespective of the frequency level and the number of mounted memory devices.Type: GrantFiled: July 29, 2002Date of Patent: January 10, 2006Assignees: Elpida Memory, Inc., Hitachi Tohbu Semiconductor, Ltd., Hitachi, Ltd.Inventors: Yoji Nishio, Seiji Funaba, Kayoko Shibata, Toshio Sugano, Hiroaki Ikeda, Takuo Iizuka, Masayuki Sorimachi -
Patent number: 6946306Abstract: A method of manufacturing a semiconductor device able to reduce the number of manufacturing steps and attain the rationalization of a manufacturing line is disclosed. The semiconductor device is a high-frequency module assembled by mounting chip parts (22) and semiconductor pellets (21) onto each of wiring substrates (2) formed on a matrix substrate (27) after inspection. A defect mark (2e) is affixed to a wiring substrate (2) as a block judged to be defective in the inspection of the matrix substrate (27), then in a series of subsequent assembling steps the defect mark (e) is recognized and the assembling work for the wiring substrate (2) with the defect mark (2e) thereon is omitted to attain the rationalization of a manufacturing line.Type: GrantFiled: November 9, 2004Date of Patent: September 20, 2005Assignees: Renesas Technology Corp., Hitachi Tohbu Semiconductor, Ltd.Inventors: Akio Ishizu, Kazutoshi Takashima, Shiro Oba, Yoshihiko Kobayashi, Tsutomu Ida, Shigeru Haga, Susumu Takada, Iwamichi Koujiro, Norinaga Arai, Yuji Kakegawa
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Patent number: 6943441Abstract: In a semiconductor device such as a high-frequency power amplifier module, a plurality of amplifying means are formed on a semiconductor chip which is mounted on a main surface of a wiring substrate, and electrodes of the semiconductor chip are electrically connected by wires to electrodes of the wiring substrate. In order to make the high-frequency power amplifier module small in size, a substrate-side bonding electrode electrically connected to a wire set at a fixed reference electric potential is placed at a location farther from a side of the semiconductor chip than a substrate-side output electrode electrically connected to an output wire. A substrate-side input electrode electrically connected to an input wire is located at a distance from the side of the semiconductor chip about equal to the distance from the side of the semiconductor chip to the substrate-side output electrode, or at a location farther from the side of the semiconductor chip than the substrate-side bonding electrode is.Type: GrantFiled: November 12, 2002Date of Patent: September 13, 2005Assignees: Renesas Technology Corp., Hitachi Tohbu Semiconductor, Ltd.Inventors: Iwamichi Kohjiro, Yasuhiro Nunogawa, Sakae Kikuchi, Shizuo Kondo, Tetsuaki Adachi, Osamu Kagaya, Kenji Sekine, Eiichi Hase, Kiichi Yamashita
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Patent number: 6900604Abstract: A drive control system, with PLL control, drives a rotatable multi-phase sensor-less motor by switching a current of a field coil of each phase depending on the rotating phase of the motor. When the moto is driven, a desired phase is selected as a datection phase, and a voltage induced on the coil of the detection phase is detected when power is fed for a predetermined time to the field coils other than the detection phase. A magnetic pole position is detected from the amplitude condition of the detected induced voltage. Based on this detection, the power-feeding phase of the motor drive is determined. Power feeding and pole position detection are performed alternately.Type: GrantFiled: November 12, 2002Date of Patent: May 31, 2005Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Hitachi Tohbu Semiconductor, Ltd.Inventors: Yasuhiko Kokami, Kunihiro Kawauchi, Toshiyuki Tsunoda, Reiichi Kimura
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Patent number: 6897728Abstract: A high frequency power amplifier module of a multistage amplifier construction comprising: an input terminal; an output terminal; a control terminal; and a mode switching terminal. The first amplification stage includes a dual gate FET, and a bias voltage according to a signal is applied to the first gate and the second gate of the dual gate FET from the control terminal and the mode switching terminal, and a radio signal from the input terminal is applied to the second gate such as the source of the dual gate FET. In dependence upon the signal from the mode switching terminal, the mode of the high frequency power amplifier module is for the GSM (i.e., for a non-linear amplifying action) and for the EDGE (for a linear amplifying action).Type: GrantFiled: July 8, 2003Date of Patent: May 24, 2005Assignees: Renesas Technology Corp., Hitachi Tohbu Semiconductor, Ltd.Inventors: Masahito Numanami, Hitoshi Akamine, Tsuyoshi Shibuya, Tetsuaki Adachi, Masatoshi Morikawa, Yasuhiro Nunogawa
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Patent number: 6841770Abstract: An AD-converted digital video data is encoded by a difference encoding method before it is outputted and such encoded digital video data is then outputted, after it is converted to gray code or to a predetermined code in which a fixed value is added. Problems solved include noise that is generated when the AD conversion circuit outputs video data and that migrates into a CCD side via a power supply line on a printed circuit board, and noise that appears on a display image by migration into an input terminal side from an output circuit side via the power supply line and a semiconductor substrate within an AD conversion LSI.Type: GrantFiled: April 5, 2004Date of Patent: January 11, 2005Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Hitachi Tohbu Semiconductor, LtdInventors: Yasutoshi Aibara, Hiroki Nakajima, Eiki Imaizumi, Tatsuji Matsuura