Abstract: It is desirable to prevent breakage and separation of wiring of a semiconductor integrated circuit device, such as a bit-line of a DRAM. To accomplish this, an HDP silicone oxide film is deposited on a bit-line that is connected to the source and drain region of a memory cell selection MISFET of a DRAM memory cell by means of a high density plasma CVD technique, and the structure is subjected to RTA (heat treatment) at 750° C. The surface is polished, and then a capacitor to be connected to the other of the source and drain region of the memory cell selection MISFET is formed. As a result, even when a tantalum oxide film, that serves as a capacitance insulating film of the capacitor, is subjected to heat treatment, the film stress exerted on the bit-line is reduced, and breakage and separation of the bit-line are prevented.

Abstract: An image input system comprises a solid state image pickup device and a preprocessor (3) for performing correlated double sampling amplification on an output signal of the solid state image pickup device and outputting a video signal. The preprocessor comprises: a correlated double sampling amplifier (30) for outputting signal information corresponding to a difference voltage between the black level in a feedthrough period of the solid state image pickup device and a signal level in a charge signal output period; and offset cancelling means (38) for applying an offset cancelling voltage for cancelling an offset voltage corresponding to the difference voltage between the black level and the signal level in a state where the solid state image pickup device is optically interrupted to the input terminal of the correlated double sampling amplifier. The correlated double sampling amplifier cancels out the offset voltage and the offset cancelling voltage as signal components of polarities opposite to each other.

Abstract: Currents of sine waveforms can be fed through coils by a relatively small-sized circuit, and thereby, highly dense magnetic storage can be realized with less rotation variations and a driving control circuit of a motor rotating at a low noise level can be provided. A coil of one phase of a three-phase brushless motor is driven with full amplitude at which an applied voltage becomes equal to a source voltage, and a coil of one of other phases is driven with gradually changing voltages so that a current of sine waveform is delivered, and a coil of the remaining phase is driven by feedback control so that a total current flowing through all coils becomes a predetermined current value.

Abstract: An AD-converted digital video data is encoded by a difference encoding method before it is outputted and such encoded digital video data is then outputted, after it is converted to gray code or to a predetermined code in which a fixed value is added. Problems solved include noise that is generated when the AD conversion circuit outputs video data and that migrates into a CCD side via a power supply line on a printed circuit board, and noise that appears on a display image by migration into an input terminal side from an output circuit side via the power supply line and a semiconductor substrate within an AD conversion LSI.

Abstract: An AD-converted digital video data is encoded by a difference encoding method before it is outputted and such encoded digital video data is then outputted, after it is converted to gray code or to a predetermined code in which a fixed value is added. Problems solved include noise that is generated when the AD conversion circuit outputs video data and that migrates into a CCD side via a power supply line on a printed circuit board, and noise that appears on a display image by migration into an input terminal side from an output circuit side via the power supply line and a semiconductor substrate within an AD conversion LSI.

Abstract: A memory module MM, in which a module wiring substrate 5 is equipped with function switching means KK1 and KK2 for arbitrarily switching function switching signals to be inputted to function switching pins FP0 and FP1 of memories 1. By these function switching means KK1 and KK2, moreover, the function switching signals are arbitrarily switched from any of no connection, a supply voltage Vcc and a ground potential Vss. These signals are inputted altogether to all the mounted memories 1 to switch and arbitrarily set functions including reading modes and refresh cycles.

Abstract: An image input system includes a solid state image pickup device and a preprocessor for performing correlated double sampling amplification on an output of the image pickup device and outputting a video signal. The preprocessor has a correlated double sampling amplifier for outputting signal information corresponding to a difference voltage between the black level in a feedthrough period of the image pickup device and a signal level in a charge signal output period; and an offset cancelling circuit for cancelling an offset voltage corresponding to the difference voltage in a state where the image pickup device is optically interrupted to the input terminal of the correlated double sampling amplifier. The correlated double sampling amplifier cancels out the offset voltage and the offset cancelling voltage as signal components of polarities opposite to each other, so that circuits following the correlated double sampling amplifier are not influenced by the offset voltage.

Abstract: In an imaging system having a semiconductor integrated circuit device, noise problems due to a large through-current in an output circuit resulting from the change-over of digital video data outputted from an AD conversion LSI are reduced by a technique involving encoding and code conversion. After AD conversion of an analog color video signal from an imaging element, a difference between codes of adjacent pixels is obtained in regard to the same color, and an output code of this difference is converted into a code with less change-over bits between the adjacent codes.

Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.

Abstract: A drive control system, with PLL control, drives a rotatable multi-phase sensor-less motor by switching a current of a field coil of each phase depending on the rotating phase of the motor. When the motor is driven, a desired phase is selected as a detection phase, and a voltage induced on the coil of the detection phase is detected when power is fed for a predetermined time to the field coils other than the detection phase. A magnetic pole position is detected from the amplitude condition of the detected induced voltage. Based on this detection, the power-feeding phase of the motor drive is determined. Power feeding and pole position detection are performed alternately.

Abstract: A memory TCP loaded with four chips (1-bank 16-bit type) is constructed by a tape of one two-layer wiring layer structure, four chips mounted to this tape, etc. Common signal terminals are arranged on one set of two opposed sides, and an independent signal terminal is arranged on another side. The common signal terminals on the two sides are electrically connected to each other common signal wiring. Further, in a DIMM in which this memory TCP is mounted to front and rear sides of a substrate, plural external terminals are formed on one long side of the rectangular substrate, and the memory TCP is mounted such that the independent signal terminal of the memory TCP is arranged along an arranging direction of these external terminals.

Abstract: In a semiconductor device, the likely occurrence of cracking of a ceramic substrate, and the consequential disconnection of internal layer wiring, due to thermal changes suffered when the semiconductor device is mounted on external wiring boards having different thermal expansion is prevented. The semiconductor device has a ceramic substrate, a wiring pattern formed on a first principal plane and having mounted semiconductor components, an external electrode portion formed on a second principal plane and connected to an external circuit, internal layer wiring formed inside said ceramic substrate to electrically connect said wiring pattern and said external electrode portion via through-hole wiring, and semiconductor components and a resin layer covering said semiconductor components, wherein the internal layer wiring is formed internally with respect to the side of said ceramic substrate with a clearance of at least 0.05 mm.

Abstract: First and second pre-processing flip-flops latch a command/address signal inputted to a register by a clock having a frequency of ½ of an external clock signal and an inverse clock thereof. Thus, the command/address signal is decomprossed to a set of signals which temporarily has two times. For example, one of the set of signals has only data contents of an odd-th command/address signal, and the other has only data contents of an even-th command/address signal. Since the set of signals has twice periods of the command/address signal, first and second post-processing flip-flop can latch signals in accordance with an internal clock signal generated by a delay locked loop circuit in a state in which a set-up time and a hold time are sufficiently assured.

Abstract: A high frequency power amplifier module of a multistage amplifier construction comprising: an input terminal; an output terminal; a control terminal; and a mode switching terminal. The first amplification stage includes a dual gate FET, and a bias voltage according to a signal is applied to the first gate and the second gate of the dual gate FET from the control terminal and the mode switching terminal, and a radio signal from the input terminal is applied to the second gate such as the source of the dual gate FET. In dependence upon the signal from the mode switching terminal, the mode of the high frequency power amplifier module is for the GSM (i.e., for a non-linear amplifying action) and for the EDGE (for a linear amplifying action).

Abstract: A high frequency power amplifying apparatus is provided with an amplifying section with a plurality of amplifying stages connected in cascade. A power control signal is supplied to the amplifying section through a control terminal so as to control the output of the high frequency power amplifying apparatus. Each of the amplifying stages has a gain smaller than that of a preceding stage. Gain control signals generated from the power control signal are supplied to the respective amplifying stages. Dividing resistors are connected in series with one another between the control terminal and a reference potential so as to divide the voltage of the power control signal to thereby generate a plurality of different gain control signals. Different ones of the gain control signals are supplied to the respective amplifying stages, an absolute value of a voltage of the gain control signal applied to each stage is smaller than that applied to an earlier preceding stage.

Abstract: A DC power supply device comprises an AC/DC converter 1, a DC/DC converter 2, and a DC converter 3 converting DC power from a battery 4 to DC voltage for connecting to output terminals of the AC/DC converter. The DC power supply device is provided with a controlling circuit 100 which observes a charging control level and a load sharing level, impresses a charging command on a UPS controlling part controlling the DC converter, and simultaneously provides a PFC controlling part controlling the AC/DC converter with a current command when a voltage level is less than the charging control level, stops only the charging command when the voltage level is more than the charging level and less than the load sharing level, and provides the UPS controlling part and the PFC controlling part with current commands when the voltage level is more than the load sharing level.

Abstract: A high frequency power amplifier module of a multistage amplifier construction comprising: an input terminal; an output terminal; a control terminal; and a mode switching terminal. The first amplification stage includes a dual gate FET, and a bias voltage according to a signal is applied to the first gate and the second gate of the dual gate FET from the control terminal and the mode switching terminal, and a radio signal from the input terminal is applied to the second gate such as the source of the dual gate FET. In dependence upon the signal from the mode switching terminal, the mode of the high frequency power amplifier module is for the GSM (i.e., for a non-linear amplifying action) and for the EDGE (for a linear amplifying action).

Abstract: A DC power supply device comprises an AC/DC converter 1, a DC/DC converter 2, and a DC converter 3 converting DC power from a battery 4 to DC voltage for connecting to output terminals of the AC/DC converter. The DC power supply device is provided with a controlling circuit 100 which observes a charging control level and a load sharing level, impresses a charging command on a UPS controlling part controlling the DC converter, and simultaneously provides a PFC controlling part controlling the AC/DC converter with a current command when a voltage level is less than the charging control level, stops only the charging command when the voltage level is more than the charging level and less than the load sharing level, and provides the UPS controlling part and the PFC controlling part with current commands when the voltage level is more than the load sharing level.

Abstract: Route nets having at least one current path through which a current flows are extracted from among a plurality of route nets each representing a line that interconnects elements of an electronic circuit in electrical connecting relationship from information on an electronic schematic. The extracted route nets is separated into a first subnet of lines where currents flow and a second subnet of lines where no currents flow. A route is determined for each of the first and second subnets. Points on the routes for the first and second subnets are interconnected by another route.

Abstract: Two memory chips each being subjected to memory accesses in 2-bit units are assembled into a stacked structure by placing their back surfaces one over the other, so as to make memory accesses in 4-bit units. A memory module is so constructed that a plurality of such semiconductor storage devices, in each of which two memory chips each being subjected to memory accesses in 2-bit units are assembled into a stacked structure by placing their back surfaces one over the other, so as to make memory accesses in 4-bit units, are mounted on a mounting circuit board which is square and which is formed with electrodes along one latus thereof.