Abstract: A static memory cell is connected with word lines and data lines. First and second switches are connected in series between a data line and on output circuit. A sense amplifier has an input/output terminal connected to a common connection point of the said first and second switches. The first switch is turned off in synchronism with commencing operation of the sense amplifier such that the parasitic capacitance of the data line as viewed from the sense amplifier decreases. The second switching means is turned on a predetermined time later in order to transmit the output signal of the sense amplifier to the output circuit.

Abstract: A signal transmission circuit in which a signal is converted into two complementary signals which are outputted from a signal transmission circuit via series resistors. The amplitude of each of the complimentary signals is reduced by the series resistors and terminating resistors provided on a signal receiving side. The signal receiving side shifts the level of the signals which it inputs. The level shifted signals are amplified by a high-input impedance differential amplifying circuit.

Abstract: Means for changing-over address signals is provided in an address input portion, and the order of the signals to be input to an address decoder is changed according to external control signals. Alternatively, a reading output circuit is provided which reads data in bit unit different from that of the writing input circuit. Thus, data can be read and written even when the number of bits of data differs between in case of accessing a built-in memory of an LSI inside the LSI and in case of accessing it from outside the LSI.

Abstract: According to the present invention, as improvement in the adhesion of inner leads with a packaging resin in a resin-sealed semiconductor device is attained by spreading leads on or near the circuit-forming face of a pellet, or on or near the main non-circuit-forming face of the pellet to extend the lengths of the inner leads on or under the pellet.

Abstract: A multichannel digital signal processor includes a plurality of sets of analog-to-digital (A/D) and digital-to-analog (D/A) conversion portions. Predetermined ones of the plurality of A/D and D/A conversion portions are selected in accordance with processing steps or with the required precision of the digital signal processing.

Abstract: A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.

Abstract: A method of manufacturing a semiconductor device wherein the back surface of a semiconductor chip is adhered closely to a substrate or a seal member through a soldering material or the like, and a metallized layer is formed on the back surface of the chip for attaining good adhesion. The metallized layer according to the present invention is a layer formed by laminating a metal silicide, a barrier metal and an oxidation preventing metal successively on the back of the chip. The layer of the metal silicide can be formed in a known heat treatment process, for example, simultaneously with the formation of bump electrodes, on a main surface of the semiconductor chip by the heat used at the time of forming such bump electrodes, or simultaneously with the mounting of the semiconductor chip by the heat used at the time of the chip mounting.

Abstract: A semiconductor integrated circuit memory structure is provided which uses macro-cellulated circuit blocks that can permit a very large storage capability (for example, on the order of 64 Mbits in a DRAM) on a single chip. To achieve, this, a plurality of macro-cellulated memory blocks can be provided, with each of the memory blocks including a memory array as well as additional circuitry such as address selection circuits and input/output circuits. Other peripheral circuits are provided on the chip which are common to the plurality of macro-cell memory blocks. The macro-cell memory blocks themselves can be formed in an array so that their combined storage capacity will form the large overall storage capacity of the chip. The combination of the macro-cell memory blocks and the common peripheral circuitry for controlling the memory blocks permits a faster and more efficient refreshing operation for a DRAM. This is enhanced by a LOC (Lead On Chip) arrangement used in conjunction with the memory blocks.

Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s

Abstract: A static memory cell is connected with word lines and data lines. First and second switches are connected in series between a data line and an output circuit. A sense amplifier has an input/output terminal connected to a common connection point of the said first and second switches. The first switch is turned off in synchronism with commencing operation of the sense amplifier such that the parasitic capacitance of the data line as viewed from the sense amplifier decreases. The second switching means is turned on a predetermined time later in order to transmit the output signal of the sense amplifier to the output circuit.

Abstract: A technique for producing a chip mount type package or a TAB package with high reliability, without use of a flux which would cause environmental pollution or would hinder an enhancement of reliability, more particularly pertains to a method of irradiating bonding surfaces, for which a solder is used, and solder bump electrodes of a package with an atomic or ion energy beam, and bonding the bonding surfaces to each other under normal pressure (about 1 atm) in a continuous apparatus.

Abstract: A method of fabricating a second semiconductor integrated circuit device includes steps of forming a first semiconductor integrated circuit device which has a microcomputer and is furnished with an EPROM; determining a program for controlling the microcomputer and to be set in the EPROM (performing an initial evaluation) while information is being written into and erased from the EPROM built in the first semiconductor integrated circuit device; and thereafter forming a second semiconductor integrated circuit device in which the EPROM of the first semiconductor integrated circuit device is replaced with a mask ROM. In replacing the EPROM with the mask ROM, the peripheral circuits required for both the EPROM and the mask ROM have their circuit arrangements held basically the same, and specific peripheral circuits for use in only the EPROM have their circuit regions left as they are as logically inactive regions.

Abstract: A data output buffer is provided in connection with a semiconductor memory, such as a pseudostatic RAM, which is capable of high speed operation with respect to memory data readout. The buffer includes a latch circuit comprising a pair of NAND gate circuits having input and output terminals connected in cross connection, a pair of precharge MOSFETs provided respectively between the noninverted and inverted input terminals of the latch circuit, a pair of CMOS NAND gates which transfer the inverted signal of the latch circuit according to an inverted timing signal and a pair of series-connected MOSFETs effecting a pull-up/pull-down arrangement which receives the inverted signal of the output signal of the NAND gates.

Abstract: A static random access memory (RAM) includes a data set circuit (DSC) coupled to pairs of load elements of memory cells to test the connection between a pair of load elements and a pair of memory nodes of each of the memory cells. The data set circuit responds to predetermined control signals and data to be set to the memory cells and supplies the predetermined voltage corresponding to such data to the pair of load elements. If the pair of load elements and the memory nodes of a memory cell are properly coupled, data of the memory cell will be inverted. Therefore, if the data of a memory cell is not inverted during the test, it can be quickly determined that a disconnection fault exists at that memory cell location.

Abstract: A semiconductor integrated circuit device is provided which includes a memory cell array located in a generally central area of a semiconductor substrate with peripheral circuits located at both ends of the semiconductor substrate. A wiring layer is also provided which couples the peripheral circuits to one another. This wiring layer is arranged to have a double-layer structure of first and second aluminum layers which are electrically coupled to one another.

Abstract: A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as curent signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.

Abstract: In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.

Abstract: A main memory is subdivided into a shared region to undergo a write access from a plurality of processors and an input/output device and a plurality of private regions to undergo a write access only from the associated processor. Each of the cache devices includes a region discriminating circuit for determining whether an address generated from the processor is to be employed for an access to the shared region or to the private regions. If the access is to be conducted to the shared region, the cache devices operate according to the write-through method. On the other hand, if the access is to be conducted to the private region, the cache devices operate according to the copy-back method. When the processor or the input/output device rewrites data in the shared region of the main memory, the stored data of the shared region in the cache device of the processor is invalidated.

Abstract: In order to obtain a highly stable SRAM cell having a small cell area, a cell ratio R is set to be R=(W.sub.DEFF /L.sub.DEFF)/(W.sub.TEFF /L.sub.TEFF)<3 where L.sub.DEFF and W.sub.DEFF denote an effective channel length and an effective channel width of two driver MOSFETs 3 and 4 respectively, and L.sub.TEFF and W.sub.TEFF denote an effective channel length and an effective channel width of two transfer MOSFETs 5 and 6 respectively. Further, a maximum current I.sub.R flowing into the active loads MOSFETs 1 and 2 is set to be greater than a current I.sub.L (1.times.10.sup.-8 A) that flows into the driver MOSFET 5 when a threshold voltage is applied across the gate and the cource of the MOSFET 5. The pair of active load MOSFETs 1 and 2 are stacked on the driver MOSFETs 3 and 4 and on the transfer MOSFETs 5 and 6.

Abstract: A semiconductor memory device has a plurality of memory blocks, each block including a matrix arrangement of a plurality of nonvolatile memory elements. The device is also provided with at least one redundant data line which is selectively employed in place of a defective data line associated with a defective address in a memory block. The data lines corresponding to the respective memory blocks are selectively coupled to corresponding ones of first common data lines by a Y selector circuit in accordance with outputs of a first Y decoder, while a redundant data line is controllably coupled to a redundant common data line by a redundant selector circuit in accordance with an output of a redundant decoder.