Abstract: A semiconductor memory wherein an operating mode is selectively set by effecting bonding with respect to predetermined pads provided on a common semiconductor substrate in a predetermined combination or by cutting off predetermined fuse means provided on the common semiconductor substrate in a predetermined combination and a bit pattern is selectively set by changing a part of a photomask applied to the common semiconductor substrate.

Abstract: A semiconductor memory device is provided which includes a plurality of word line drivers and logic decoding circuitry coupled to the inputs of the word line drivers. In large memory arrays, the word line driver circuits can place large capacitive loads on the output of the logic decoding circuit because the word line driver transistors must be relatively large. This large load on the logic decoding circuitry adversely effects the operating speed of the memory. Accordingly, to reduce this load, a switching arrangement is provided between the output of the logic decoding circuitry and the word line drivers. This switching arrangement can be controlled to respectively connect the output of the logic decoding circuit to the word line drivers based on control output signals of a pre-decoder. Reset MOSFETs can also be provided to prevent the inputs of the word line drivers from floating.

Abstract: A semiconductor memory is provided with a first memory cell group, a second memory cell group, a first register for a serial output operation for holding information related to the first memory cell group, a second register for a serial output operation for holding information related to the second memory cell group, and transfer means for transferring information related to either the first or second memory cell group to either the first or second serial output register. By virtue of this arrangement, while the information transferred to the first serial output register is being serially output therefrom, information can simultaneously be transferred to the second serial output register by the transfer means.

Abstract: According to the present invention, as improvement in the adhesion of inner leads with a packaging resin in a resin-sealed semiconductor device is attained by spreading leads on or near the circuit-forming face of a pellet, or on or near the main non-circuit-forming face of the pellet to extend the lengths of the inner leads on or under the pellet.

Abstract: A dynamic type RAM is provided wherein the level of a precharge control signal supplied to a gate of a precharge MOSFET to precharge complementary data lines to a half level is made the half level during a period from the memory access until the selection of the word line, at the latest. Also, the precharge control signal, corresponding to a memory mat selected according to establishing of an address, is set to a low level, while the precharge control signal corresponding to a non-selective memory mat is set to a high level.

Abstract: A semiconductor memory device comprising a decoder circuit for selecting one divided word line from among a plurality of divided word lines; the decoder circuit including a first drive MOSFET which is arranged so as to be shared by a plurality of memory blocks each having the divided word lines with memory cells respectively coupled thereto and which receives signals to be supplied to main word lines, second drive MOSFETs which are respectively coupled to the first MOSFET in series so as to share it and which receive respective predecode signals corresponding to the plurality of divided word lines, a plurality of load means which are respectively coupled to drains of the second drive MOSFETs, and inverter circuits which invert phases of drain output signals of the respective second drive MOSFETs and transmit the inverted signals to the corresponding divided word lines.

Abstract: According to the present invention, a semiconductor chip is mounted on a zigzag in-line type package (ZIP) partially using a tabless lead frame and bonding pads are arranged on the chip so that the chip can be applied also to other different types of packages. As different types of packages there are a small out-line J-bent type package (SOJ) for which there is used a lead frame with tab and a dual in-line type package (DIP) for which there is used a tabless lead frame. Further, a plurality of bonding pad pairs are provided among the bonding pads on the chip each pad of such bonding pad pairs having the same function as the other pad associated therewith thereby duplicating a common function in different bonding pads on the semiconductor chip so as to readily facilitate, or make compatible, the semiconductor chip to a variety of or different types of packages.

Abstract: A mask-programmed ROM includes depletion type load MOSFETs provided between data lines in a memory array and a power supply voltage, the MOSFETs having a ground potential of the circuit applied to their gates. Reading of data is carried out by an amplifying MOSFET which supplies a current to a selected data line through a depletion type MOSFET which is supplied at its gate with the circuit ground potential. Thus, bias voltages which are respectively applied to the data lines and a sense amplifier which receives a signal read out from a selected data line are made equal to each other, thereby achieving a high-speed read operation.

Abstract: Information read out from a memory cell of a static type semiconductor memory is subjected to multi-stage sense amplification in an initial stage sense amplifier, a post-stage snese amplifier and a main amplifier and then transmitted to the input of an output buffer circuit. Since an equalizing circuit is connected to the complementary inputs of each stage of the multi-stage sense amplifier, an inverse information read operation can be executed at high speed. Initially, the initial stage sense amplifier, the post-stage sense amplifier and the main amplifier are controlled to operate in high amplification gain conditions so as to execute high speed sense amplification and thereafter controlled to operate in such low power consumption conditions that the read-out information output obtained by the high speed sense amplification will not disappear.

Abstract: Plural pairs of complementary data lines coupled with plural memory cells are precharged to a positive source voltage level and a pair of common complementary data lines corresponding to the plural pairs of complementary data lines are precharged to ground potential. In synchronism with selection of a word line, a pair of the plural pairs of complementary data lines and the common complementary data lines are coupled through a switch circuit. A sense amplifier coupled with the common complementary data lines is supplied with a voltage composed of a voltage of approximately half the voltage value of the positive supply voltage and a readout voltage from the memory cell superposed thereon. Thus, after the precharging operation, there is no need for an equalizing operation before a word line is selected. Therefore, high-speed reading can be achieved.

Abstract: A semiconductor memory device includes an input circuit and an output circuit. To prevent the erroneous operation of the input circuit by the noise which develops at the time of the change of the output signal of the output circuit, the threshold voltage of the input circuit is changed, or an internal signal generated by the internal circuit is fixed to a predetermined level. In an output circuit having a tri-state output function, the threshold voltage of the input circuit is changed when the output is brought into the high impedance state, or the internal signal generated by the input circuit is fixed to a predetermined state. Using these arrangements it is possible to prevent the erroneous operation of the input circuit by the noise occurring when the output is brought into the high impedance state.

Abstract: A semiconductor memory is provided in which a column decoder is used commonly for the random input and output and the serial input/output by providing both a signal path for transmitting signals in parallel to the data lines of a memory array and a latch circuit and a switch path for connecting said latch circuit and a serial input/output common data line in response to a selection signal generated by a shift register, and by feeding the output signal of a random input/output column decoder as an initial value to the individual bits of said shift register.

Abstract: A semiconductor memory having a memory array, a first and a second selection line which are connected to a memory cell, and a selection means which selects either one of the selection lines. The selection means includes a selection circuit which optionally selects the first selection line or the second selection line when an address signal corresponding to the first selection line is aligned with a predetermined address signal.

Abstract: In duplicated equipment including main equipment, duplicated subordinate equipment, and a communication line for transferring data between the main equipment and the duplicated subordinate equipment and for sending a changeover signal which can put one and the other of a pair of subordinate devices making up the duplicated subordinate equipment in an active state and a standby state, respectively, from the main equipment to the duplicated subordinate equipment, each of the subordinate devices includes means for putting the other subordinate device in the standby state, to prevent both of the subordinate devices from being put in the active state when a failure occurs on a transmission path between the communication line and one of the subordinate devices.

Abstract: An A/D converter apparatus comprises: a sampling signal generating means to generate an oversampling signal and an internal sampling signal; a converter means to convert an input analog signal into a digital signal in synchronism with the oversampling signal; and a decimator means to perform a specified decimation on the digital signal in synchronism with the internal sampling signal; whereby the sampling signal generating means maintains the frequencies of the oversampling signal and the internal sampling signal in a specified relationship.

Abstract: A dynamic RAM is provided in which an output voltage of a booster circuit for forming a word line selection timing signal is rendered greater than a power source potential and less than a predetermined potential by providing voltage limitation means, thereby preventing destruction of circuit elements receiving the output voltage.

Abstract: A mask-programmed ROM includes depletion type load MOSFETs provided between data lines in a memory array and a power supply voltage, the MOSFETs having a ground potential of the circuit applied to their gates. Reading of data is carried out by an amplifying MOSFET which supplies a current to a selected data line through a depletion type MOSFET which is supplied at its gate with the circuit ground potential. Thus, bias voltages which are respectively applied to the data lines and a sense amplifier which receives a signal read out from a selected data line are made equal to each other, thereby achieving a high-speed read operation.

Abstract: A semiconductor memory incorporating an ECC circuit includes a memory array, means for selecting a plurality of bits which are to be simultaneously output to the outside of the IC from a plurality of bits which are simultaneously read out from the memory array, and an error correcting circuit which constitutes the ECC circuit. The selecting means is provided in a stage previous to the error correcting circuit. In consequence, it is possible to reduce the number of bits of a signal which need to be simultaneously processed by the error correcting circuit. Accordingly, the size of the ECC circuit can be reduced.

Abstract: In a serial-parallel A/D converter, at least two sets of comparators are provided for the conversion of the low-order bits and are operated in a cyclic fashion. Since the subsequent input can be subjected to the A/D conversion without waiting for the determination of the low-order bits, the conversion speed is increased.