Abstract: An electronic assembly is made up of a number of electronic components. Each of the electronic components having a means for putting the component in a quiescent state while the remaining components are in a functional state, thereby enabling the testing of individual components without disassembly.

Abstract: In a computer system having at least a bus with at least one central processing unit (CPU), one random access memory (RAM), and a first configuration of a plurality of different types of peripheral units (e.g. tape drives, disk drives, diskette drives, printers, unit record peripherals, etc.) coupled to the bus, an apparatus for controlling the first configuration and also capable of controlling a predetermined number of other configurations of different types of peripheral units when any of that predetermined number of configurations of peripheral units is coupled to the bus.

Abstract: An apparatus is included within the bus interface circuits of each processing unit of a multiprocessing system which connect in common with the other units of the system to an asynchronous system bus. The apparatus and interrupt signal couple to the processing unit's level register and interrupt circuits. In response to a command specifying a level change, the apparatus conditions these circuits to store level and interrupt signals applied to the system bus as part of such CPU command during a bus cycle of operation granted to the processing unit on a priority basis. This ensures the reliable switching between interrupt levels and the notification of such level changes to the other units of the system without interference from other processing units.

Abstract: An address path which transfers addresses from a number of sources includes an incrementing circuit. The address includes a plurality of address bits and integrity bits. The address bits are applied to the incrementing circuit while the integrity bits are applied in parallel to a programmable logic device (PLD). While the address is being transferred or incremented as required, the PLD independently generates a number of transform bits defining a characteristic of the number of address bits predicted to change state. Thereafter, the transform bits are used to transform the address integrity bits for transfer with the incremented address. The incremented address, transform bits and integrity bits are logically combined for verifying that the address was transferred and/or incremented without error.

Abstract: A binary arithmetic unit performs arithmetic operations on binary coded decimal (BCD) operands by converting the BCD digits to hexadecimal excess 3 digits, generating hexadecimal excess 6 partial product digits and modifying selected excess 6 partial product digits to generate a BCD result.

Abstract: A microprocessor integrated circuit chip includes a plurality of functional areas containing a large number of widely distributed signal sources. An on-chip selection network is distributed on the chip which enables the selection of signals from the large number of sources under microinstruction control without any decrease in chip performance. The network includes an access bus which is distributed to the functional areas as a function of the concentration of signals provided by the sources. Individual decoders are strategically located on the chip and connect in common to a control bus. Each decoder connects to a plurality of switches for linking the sources of a functional area to the access bus. A selector circuit terminates the access bus at one end. Under microprogram control, the selector circuit is enabled to select which final source signal is applied to the functional area containing branching circuits for selecting a next microinstruction to be executed by the microprocessor.

Abstract: A computer system includes a first processor with main memory, an input/output processor with associated memory and an archival memory. Prior to reloading a new operating system from archival memory into the main memory, information such as timer information is stored in the input/output memory. The input/output memory continues to update the timer information until the second operating system is bootstrap loaded into the main memory. The timer and other information may then be returned to the first processor and main memory for use by the second operating system.

Abstract: A printer apparatus having two-sided printing capability is taught. Two printing mechanisms are provided that can simultaneously print both sides of roll paper. The printing mechanisms are physically oriented with respect to each other and to a simple paper handling/routing mechanism comprised of rollers so that when only one printing mechanism is installed to provide only one-sided printing, the paper handling mechanism need not be modified but the roll paper is merley routed differently around the rollers. Retroactively, a second printing mechanism may simply be installed in the printer for two-sided printing and the roll paper is routed around the rollers differently to route the roll paper to and from the second printing mechanism.

Abstract: A method for determining the maximum amount of physical memory present in a data processing system that can be configured to have one or more memory modules where the memory modules may be one of several types having different amounts of memory locations. By having signals indicating the presence of a memory module and the module type directly available with minimal intervening logic, a diagnostic process can accurately determine the amount of memory present in the system and reduce the possibility of a failed memory module going undetected. A method is also descibed using these memory module present and module type signals for detecting an attempt by either the central processor or an input/output controller to access a memory location that is not physically present within the data processing system.

Abstract: A cache memory subsystem has multilevel directory memory and buffer memory pipeline stages shared by at least a pair of independently operated central processing units. For completely independent operation, each processing unit is allocated one-half of the total available cache memory space by separate accounting replacement apparatus included within the buffer memory stage. A multiple allocation memory (MAM) is also included in the buffer memory stage. During each directory allocation cycle performed for a processing unit, the allocated space of the other processing unit is checked for the presence of a multiple allocation. The address of the multiple allocated location associated with the processing unit having the lower priority is stored in the MAM allowing for earliest data replacement thereby maintaining data coherency between both independently operated processing units.

Abstract: A multiprocessor computer system includes a main memory and a plurality of central processing units (CPU's) which are connected to share main memory via a common bus network. Each CPU has instruction and data cache units, each organized on a page basis for complete operating compatibility with user processes. Each cache unit includes a number of content addressable memories (CAM's) and directly addressable memories (RAM's) organized to combine associative and direct mapping of data or instructions on a page basis. An input CAM in response to a CPU address provides a cache address which includes a page level number for identifying where all of the required information resides in the other memories for processing requests relating to the page. This organization permits the processing of either virtual or physical addresses with improved speed and reduced complexity and the ability to detect and eliminate both consistency and synonym problems.

Abstract: A method for performing margin justification in a word processing system by expanding the separation between words and between characters within words. Justifying lines of text by use of this method results in lines of text with an aesthetically pleasing uniform margin. The method uses the granular units of output devices so that one justification procedure can be used on all output devices.

Abstract: A least recently used replacement level generator is constructed to include n number of register stages connected in tandem. A comparison circuit associated with each stage except the last stage compare the contents of that stage with an input level value which is to be loaded into the input stage. In the absence of an identical comparison, each stage generates a shift enable signal which is passed on to the next succeeding stage. An identical comparison inhibits the generation of the shift enable signal. Therefore, when a clock signal is applied to the device, register stages, in the presence of a control signal, cause the input level to be loaded into the input stage while the level contents of the register stages are simultaneously shifted through successive stages including the register stage whose contents are identical to the input level under the control of the shift enable signal.

Abstract: A method and apparatus for determining if matching units of an electronic system or a subsystem are assembled includes a single scratchpad memory which is addressed by the units on alternate cycles. A microprogram stored in one unit operates in synchronism with a microprogram in the other unit to write into and to test the contents of a location in scratchpad memory to determine if the two units would be operational with each other during normal operation.

Abstract: What is disclosed is a time partitioned bus arrangement for use in a computer system wherein different circuits therein are interconnected by a plurality of busses and operation is such that information to be processed can be read out of one circuit, processed in some manner in another circuit, and the processed information be stored in the same or another circuit all within one cycle of a system clock in the computer system, and without the need for bus control circuits and bus interfaces in the circuitry connected to the busses. Some of the circuits have their input/output connected to only a single one of the busses, while other circuits have their input connected to one bus and their output connected to a different bus, and yet other circuits have either their input or output connected to one of the busses and their other input/output connected to circuitry external to the bus arrangement.

Abstract: A split bus architecture which separates the processor/processors and the procedure memory coupled to a microprocessor (.mu.P) bus from all direct memory access (DMA) devices coupled to a DMA bus. A coupler mechanism provides bus isolation of the microprocessor bus from the DMA bus and permits the processor to access devices on the DMA side when addressed. This separation allows data transfers to proceed on one side of the bus without interfereing with software execution on the other side of the bus.

Abstract: In a Distributed Database System (DDS), database management and transaction management are extended to a distributed environment among a plurality of local sites which each have transaction server, file server, and data storage facilities. The Materialization and Access Planning (MAP) method of a distributed query, update, or transaction is an important part of the processing of the query, update, or transaction. Materialization and access planning results in a strategy for processing a query, update, or transaction in the distributed database management system (DSDBMS). Materialization consists of selecting data copies used to process the query, update, or transaction. This step is necessary since data may be stored at more than one site (i.e., computer) on the network. Access planing consists of choosing the execution order of operations and the actual execution site of each operation. Three access planning methods are used: General (Response), General (Total) and Initial Feasible Solution (IFS).

Abstract: An apparatus and a method for interfacing a commercially-available programmable communication interface (PIC) with a magnetic swipe reader or a wand type reader. The invention modifies the raw signals of the magnetic wand and magnetic swipe readers by removing noise and selecting the appropriate reader and track, stretching the clock pulses of the reader, and latching data into a flip-flop until the data is strobed into the PIC.

Abstract: A cache memory subsystem couples to main memory through interface circuits via a system bus in common with a plurality of central processing subsystems which have similar interface circuits. The cache memory subsystem includes multilevel directory memory and buffer memory pipeline stages shareable by at least a pair of processing units. A read in process (RIP) memory associated with the buffer memory stage is set to a predetermined state in response to each read request which produces a miss condition to identify the buffer memory location of a specific level in the buffer memory which has been preallocated. The contents of the buffer memory stage are maintained coherent with main memory by updating its contents in response to write requests applied to the system bus by other subsystems. Upon detecting the receipt of data prior to the receipt of the requested data which would make the buffer memory contents incoherent, the cache switches the state of control means associated with the RIP memory.

Abstract: A furnace for firing a non-precious metal paste including organic material, comprising a furnace enclosure, tube-like in shape, having a definable length. First and second ends of the furnace enclosure is open forming an entrance and exit, respectively. A cross-section across the length of the furnace enclosure has a flat base, a first and second vertical wall at each end of the flat base, and a roof, the shape of the roof being essentially the upper half of an ellipse. The interior chamber of the furnace is divided across the length of the furnace enclosure into a burnout zone and a firing zone, the entrance leading to the burnout zone, and the exit being nearest the firing zone. A sparging element distributes a mixture of an inert gas and at least one other gas within the burnout zone, wherein the other gas supports burnout of the organic material.