Abstract: A data processing system includes a plurality of units which are coupled to transfer requests including data, command and integrity signals between units over a system bus during allocated bus transfer cycles. Each unit includes response apparatus for acknowledging requests received from other units. Each of a number of units further includes retry apparatus and like checking apparatus for verifying that the different parts of a request received from such unit over the bus are valid based upon the states of accompanying function identification signals. When less than all of the parts of the request defined as requiring verification are detected as valid, the receiving unit does not accept the request and inhibits its response apparatus from generating a response. This prevents damage to system integrity and permits each unit with retry apparatus to retry the request during a subsequent bus transfer cycle.

Abstract: A data processing system includes a plurality of units which are coupled to transfer requests including data, command and integrity signals between units over a system bus during allocated bus transfer cycles. Each unit includes response apparatus for acknowledging requests received from other units. Each of a number of units further includes retry apparatus and checking apparatus for verifying that all of the parts of a request received from such unit over the bus are valid. When less than all of the parts of the request are detected as valid, the receiving unit does not accept the request and inhibits its response apparatus from generating a response. This prevents damage to system integrity and permits each unit with retry apparatus to retry the request during a subsequent bus transfer cycle.

Abstract: A memory subsystem couples to a bus in common with and proceses memory requests received therefrom. The subsystem includes a single addressable memory module unit or stack having a number of word blocks of dynamic random access memory (DRAM) chips mounted on a single circuit board which connects to the remainder of the subsystem through a single word wide interface. Chip select circuits preselect a pair of blocks of RAM chips from the stack. Timing circuits generate a plurality of sequential column address pulses which are selectively applied to the preselected blocks of chips within an interval defined by a row address pulse. This results in the sequential read out of a pair of words from the preselected blocks of the single word wide module into a pair of subsystem data registers. For each memory read request, the words from each preselected pair of blocks are read out in sequence providing a double fetch capability without any loss in system performance.

Abstract: An electronic equipment housing provides easy access to electronic equipment via a hinged top panel and a clear plastic safety panel below it. Inside the housing are cable raceways located at the top front and top rear which are in line with raceways in adjacent housings to permit many cables to be contained inside the housings. The raceways and cables are positioned so as not to interfere with convection cooling inside the housings and with access to the equipment. Relatively high heat generating equipment such as power supplies are mounted to one side of the interior of the housing enabling separate fans to cool the power supplies using a single flow of air while other equipment in the housing is cooled by a separate flow of air drawn by other fans. Common system equipment is enclosed in the housing located at a predetermined one end of a series of adjacent housings.

Abstract: A display subsystem having a graphics capability includes a bit map memory for storing bits, each bit representing a displayed pixel. A read only memory stores words, each word representative of a pixel of a selected pattern which is used to fill out an area of the display thereby clearly identifying adjacent areas of the display to the operator. The selected patterns are displayed in a REPLACE, an OR or an EXCLUSIVE OR mode of operation.

Abstract: A method for printing composite characters in a word processing system by multistriking two or more characters in the same character space. This method allows composite character graphics to be produced by using individual character graphics found within the character set of the output device. The method provides for the vertical and/or horizontal offsetting of the printhead between the striking of individual characters which form the composite character.

Abstract: Local area network control block (LCB) hardware and a method is disclosed which forms a prime vehicle of intercommunication between controller coupled local area networks (LANs), comprising a plurality of computer systems. An LCB has a predetermined format and is assembled by the computer hardware to provide information to the controller regarding the routing and transfer of a variable quantity of data between LANs.

Abstract: The electronic equipment of a computer system including electronic cards, power supplies, peripheral units, cooling units and internal and external cables are compactly packaged within a small enclosure in a way which permits sufficient airflow from front to rear of the enclosure. The enclosure includes a pair of rail members located at the rear which have a plurality of mounting positions for attaching a corresponding number of modular shelf members which are angled to permit the flow of air through established airflow paths. The rail and shelf members collectively form a bulkhead structure. The rail members are offset from the sides of the frame so as to form vertical channels on each side. The channels are used for retaining external cables which plug into connectors mounted on the shelf members and are distributed so as not to interfere with airflow.

Abstract: A disk controller address register is used to address both a disk controller memory and a system memory between which data is transferred as it is stored on or retrieved from a disk storage device. A single address is provided to the address register which then develops other addresses needed in the data transfer between the two memories.

Abstract: A computer system is described wherein two independent processors communicate via a bus system and operate substantially concurrently, each computer having its own operating system software and share a common memory. The architecture of the computer system is such that one of the processors is allocated the bulk of memory band-width with the other processor taking the remainder. Arbitration for memory allocation is accomplished via a combination of a new firmware instruction and a semaphore.

Abstract: Cache memory includes a dual or two part cache with one part of the cache being primarily designated for instruction data while the other is primarily designated for operand data, but not exclusively. For a maximum speed of operation, the two parts of the cache are equal in capacity. The two parts of the cache, designated I-Cache and O-Cache, are semi-independent in their operation and include arrangements for effecting synchronized searches, they can accommodate up to three separate operations substantially simultaneously. Each cache unit has a directory and a data array with the directory and data array being separately addressable. Each cache unit may be subjected to a primary and to one or more secondary concurrent uses with the secondary uses prioritized.

Abstract: A multiple processor computer system features a store-into cache arrangement wherein each processor unit of the system has its own unique cache memory unit. Data operated upon by any one of the processor units is stored in the cache memory associated with that processor unit. When a thus modified block of data is required by another one of the processor units, the requested data is transferred directly to the requesting processor unit without having to first transfer the data to a shared main memory. Provision is also made for transferring data, under prescribed conditions from a cache to the main memory, but not as a precondition for transfer to a requesting processor.

Abstract: One of a plurality of taps of at least one transformer is selected by choosing a predetermined plug to mate with a predetermined jack. The connection arrangement between each transformer and a corresponding jack is such that each pin of a respective jack is operatively connected to a predetermined transformer tap of the corresponding transformer whereby the corresponding taps of each of the transformers are connected to different corresponding pins for each of the corresponding jacks. Further, the starting tap of each transformer is operatively connected to the same corresponding pin of the jack corresponding to the transformer. A plurality of plugs, the number of plugs corresponding to one less than the number of pins of the jacks, is included whereby each plug has a plurality of mating pins corresponding to the pins of the jack. Each mating pin of each plug which corresponds to the pin of the starting tap is operatively connected to a first supply terminal.

Abstract: A bit-string address or a multi-bit character count is converted to a real word memory address by division by a constant value. The division is accomplished without reference to an arithmetic logic unit. Division is accomplished by means of a look-up table stored in a ROM with the quotient and remainder values being stored in the ROM. The provided address, or dividend, values are used to address the ROM to determine the quotient and remainder values corresponding thereto. When the dividend values are of a dimension larger than can be divided by a single pass at the ROM, the division is accomplished by several successive passes through the ROM to provide a succession of partial quotient values. The resulting quotient and remainder values define the proper address for the computer memory.