Abstract: A memory controller in which a number of local memories are primarily dedicated to the shared use of a number of local processors of a data processing system to increase the efficiency of use of both the processors and memories. A controller is associated with each local memory to control connection of any one of the local processors to its associated local memory. A local processor can also be connected via a controller and an adapter circuit connected to the controller to a system bus to obtain access to circuits connected thereto. In addition, a system processor connected to the system bus may also be connected to any particular one of the local memories via its associated controller and adapter connected thereto to load data or programs into the local memory for use by the local processors, and to read out the results of previous processing done by the local processors.

Abstract: In a data processing system having a system controller unit (SCU) which interfaces a plurality of equipments with a memory unit, the SCU determines which of the equipments will be permitted to communicate with the SCU or memory unit in response to a request from the equipments. The SCU includes an activity monitor and control apparatus which determines whether the request from the equipments can be accepted. The activity monitor and control apparatus comprises a plurality of first elements, each of the first elements being assigned to monitor a request which has been accepted. The activity monitor and control apparatus monitors the operations with the SCU thereby providing status information of the SCU. A plurality of second elements, which is operatively connected to the first elements, combines preselected status information to generate control signals thereby indicating current and future availability of the SCU in order to determine whether a request can be accepted.

Abstract: An address boundary detector is disclosed that functions with an arithmetic logic unit (ALU) in a computer processor while the ALU generates addresses by adding an offset or displacement to a base address. The detector monitors bits of addresses to determine whether a data item can be completely stored within the same block or page of memory as that addressed by the base address from which it was derived.

Abstract: An interactive terminal system transfers information at 750,000 bits per second between a central system and a number of work stations, all coupled in common to a single conductor coaxial bus. The central system prepolls an addressed work station before sending a block of information. The prepoll conditions the work station to prepare to receive a block of information.

Abstract: A memory subsystem couples to a bus in common with a central processing unit and processes memory requests received therefrom. The subsystem includes a number of addressable memory module units or stacks each having a number of word blocks of dynamic random access memory (DRAM) chips arranged in one of two subsystem configurations and mounted on a single circuit board which connects to the remainder of the subsystem through a single word wide interface. The configurations correspond to a common stack arrangement which provides double the normal amount of density and an adjacent stack arrangement of normal density. As a function of an input density signal, chip select circuits preselect a pair of blocks of RAM chips from a common stack or pair of adjacent stacks. Timing circuits generate a plurality of sequential column address pulses which are selectively applied to the preselected blocks of chips within an interval defined by a row address pulse.

Abstract: A memory board can be assembled with one, two or more rows of memory chips to provide a corresponding number of different memory capacities for expanding the capacity of main memory which resides on a basic logic board containing the processing units and other units of a system. The memory board includes a programmable read only memory (PROM) circuit which receives as inputs from the basic logic board a predetermined address portion of each memory address together with memory refresh and timing signals. The PROM circuit is coded in a predetermined manner for generating at its output terminals row address select (RAS) pulse output signals to a row or block of memory chips designated by the predetermined address portion. The pulse widths of the output signals are established by the timing signal applied to an enabling terminal of the PROM.

Abstract: A data entry terminal for use in a hostile environment is sealed from the outside environment. The terminal has a housing made up of a front panel, shroud and base plate that are fastened together in two different orientations to facilitate desk top and wall mounting, and electronic equipment is mounted inside the terminal enclosure. A fan circulates air around the inside of the terminal enclosure for cooling the electronic equipment inside. The enclosure base acts as a heat sink to transfer the heat to the outside environment in whatever position the terminal is mounted.

Abstract: A data processing system includes a central processor unit (CPU), a main memory and a memory management unit (MMU). Information is stored in main memory in segments, each segment being identified by a segment descriptor stored in a translation table in the MMU. Logical addresses from the CPU address segment descriptors in the MMU's translation table. These segment descriptors include the physical address of the location in main memory of the first word of the segment. If the segment descriptor is not in the translation table location, then the MMU operation is suspended while the segment descriptor is demand fetched from main memory.

Abstract: In a computer system having a plurality of processors and processes, a semaphore architecture for communication with and between the processes in order to effects coordination and cooperation between processes. The invention is implemented in firmware and software, and divides the work of an entire semaphore operation such that the simple part of the P and V operations (which deliver and pick-up signals to and from the processes, respectively) is done by the firmware; whereas the difficult work of the P or V operation is done by software. Thus the improved architecture increases the speed of the system by the use of firmware and increases the flexibility of the computer system by utilizing software to change functionality.

Abstract: A data processing system has a system bus network which includes a distributed priority network for transferring data asynchronously between a number of subsystems which couple to the bus. Each subsystem includes priority logic circuits coupled to receive a group of priority signals from the priority network which establish when the subsystem has the highest priority of the requesting subsystems to access the bus. The number of subsystems include a plurality of identical subsystems, each of which has a channel number assignment apparatus. The apparatus of each identical subsystem is connected to receive the same of at least one of the group of priority signals. During the idle state of the system bus, the apparatus of each identical subsystem operates to store a unique state of the priority signal which is defined as a function of the subsystem's position on the bus thereby automatically establishing a unique channel number value for each identical subsystem.

Abstract: The invention pertains to a method and apparatus to provide for the display of characters and graphics in color. The invention includes three bit map memories which store graphics information for different colors, one character generator driven from a text memory for display of text, and an attribute memory for storing display characteristics such as inverse video and blinking. The contents of the bit map and attribute memories and the output of the character generator are used to address a pre-programmed ROM. The output from the ROM is a string of three bit words with each bit stream representing a primary color on a color CRT and being connected to the associated color input to the CRT. Composite graphics and text are displayed on the CRT.

Abstract: A method for achieving printed circuit (PC) board-level testability through electronic component-level design using available technological methods to effect a state of transparency during test, allowing precise verification and diagnosis on a component-by-component basis. Applicable to a greater variety of electronic products than other test methods, and not appreciably constraining functional design, this approach inherently avoids obstacles which prevent other techniques from fulfilling their objectives.

Abstract: In combination with a multiprocessing/multiprogramming computer system having a ring protection mechanism for protecting computer programs from unauthorized access, a new call instruction architecture is implemented partly in firmware and partly in hardware. Also, a new stack mechanism stores hardware managed control information in a control frame and software controlled data in a data frame.

Abstract: What is disclosed is a housing for a D-shell connector that comprises two housing parts that snap and lock securely together and can later be separated without the use of tools. In addition, the housing has an integral strain relief cable clamp. Internal or external latching arms capable of latching to more than one connector configuration are easily and quickly combined or charged with the basic connector housing, and one latching arm can simultaneously latch a holding to a mating connector housing and to a cutout in a chassis or panel.

Abstract: A Loadable Character Generator whose operation can be changed to suit various needs, such as foreign language requirements, without hardware change and with minimum hardware. The character generator translates the character code of a character to be displayed to the dot pattern for that particular character, utilizing a minimum of hardware. The loadable character generator of the invention replaces the ROM/PROM by a RAM utilizing 2K and 8 RAM memories, a 4K by 8 memory, 4 MUX chips, and a Motorola 6845 CRT Controller with various registers and is loaded through the attribute buffer.

Abstract: A graphics display is cleared by apparatus forcing binary ZERO's into all locations of the bit map memories between successive vertical synchronization operations during a write refresh operation.

Abstract: A bolt-on configuration of a power distribution system utilizes an apparatus which connects a first element to a second element, the second element having a hole, such that a minimum predetermined force exists at the connection between the first element and the second element. The apparatus comprises a shaft, having a first, second, and third diameter along the axis of the shaft, thereby forming a first, second, and third shaft, respectively, the first diameter being the smallest diameter and the third diameter being the largest diameter. The first shaft is threaded, for mating with the second element. A spring, having an inside diameter smaller than the diameter of the third shaft and having a length approximately equal to the length of the first and second shaft is coaxially positioned over the first and second shaft.

Abstract: A cache memory unit is constructed to have a two-stage pipeline shareable by a plurality of sources which include two independently operated central processing units (CPUs). Apparatus included within the cache memory unit operates to allocate alternate time slots to the two CPUs which offset their operations by a pipeline stage. This permits one pipeline stage of the cache memory unit to perform a directory search for one CPU while the other pipeline stage performs a data buffer read for the other CPU. Each CPU is programmed to use less than all of the time slots allocated to it. Thus, the processing units operate conflict-free while pipeline stages are freed up for processing requests from other sources, such as replacement data from main memory or cache updates.

Abstract: A pair of conductive ground clips each having a plurality of flexible fingers, are slid into an interference engagement with the ends of a flange of a D-shell connector. The ground clip equipped connector is held in a plastic connector housing which is latched to a conductive plate by flexible latching arms that are a part of the connector housing. As the connector housing is latched to the plate with the latching arms, flexible fingers on the clips touch the plate and flex making and maintaining a good electrical connection therewith. The ground clips maintain a proper electrical ground connection between the housing contained connector and the plate avoiding undesirable electrostatic discharge, electromagnetic interference, and radio-frequency interference.

Abstract: A multilevel set associative cache system whose directory and cache store are organized into levels of memory locations includes control apparatus which selectively degrades cache operation in response to error signals from directory error checking circuits to those levels detected to be free from errors. Test apparatus coupled to the control apparatus and operates to selectively alter the operational states of the cache levels in response to commands received from a central processing unit for enabling testing of such control apparatus in addition to the other cache control areas.