Patents Assigned to Honeywell Information Systems, Inc.
  • Patent number: 4586129
    Abstract: A data processing system includes a cathode ray tube (CRT) display. Apparatus associated with the CRT tests and verifies the vertical and horizontal synchronization and the logic associated with a character generator. Refresh signals, horizontal synchronization signals and data bit signals from the character generator are counted. The counts of those signals which occur within a predetermined number of occurrences of vertical synchronization signals are verified.
    Type: Grant
    Filed: July 5, 1983
    Date of Patent: April 29, 1986
    Assignee: Honeywell Information Systems Inc.
    Inventors: Thomas L. Murray, Jr., Kin C. Yu, Thomas O. Holtey
  • Patent number: 4583199
    Abstract: The present invention relates to an alignment network for aligning data words having a plurality of data word formats. A plurality of shifters are utilized, each shifter utilized to shift the corresponding bit of each character. When the output data word format is different from the input data word format, selected characters in response to a predetermined control signal are temporarily stored so that they may be inputted to the shifters on the next shift cycle in order to achieve the desired shifted character order. An alignment switch then aligns or packs the shifted data from the output of the shifters to the predetermined data format in response to a select control signal.
    Type: Grant
    Filed: July 2, 1982
    Date of Patent: April 15, 1986
    Assignee: Honeywell Information Systems Inc.
    Inventors: Donald C. Boothroyd, Robert W. Norman, Jr.
  • Patent number: 4581738
    Abstract: A test and maintenance system for use with a data processing system comprising a specialized circuit set wherein the circuit set registers can be configured into a serial array, a clock signal distribution system capable of delivering controlled clock signals to selected serial arrays, a maintenance data processor for providing predetermined signal groups, and addressing apparatus responsive to the predetermined signal groups for loading and unloading register arrays in response to the predetermined signals. The disclosed apparatus permits a predetermined signal group to be entered into the serial register array, a predetermined number of clock cycles (i.e. series of operations performed on the data), and the resulting signals shifted from the serial register array and signals applies to data processing unit for display or analysis.
    Type: Grant
    Filed: October 6, 1983
    Date of Patent: April 8, 1986
    Assignee: Honeywell Information Systems Inc.
    Inventors: Homer W. Miller, James L. King
  • Patent number: 4577400
    Abstract: A tool facilitates the hand insertion of wire wrap square sectioned pins from a fanning metal strip into plated through holes of a wire-wrap printed circuit board. The tool includes a solid cylindrical tip which is mounted within a handle member which includes an automatic anvil. An end portion of the tip has a portion with stepped profile which contains a round hole. The hole is slightly larger than the square section of the pin and has a predetermined depth for positioning the pin in a vertical direction during an insertion operation. The sizes of the individual steps are selected to enable the pins to be ejected completely from the band portions of the strip into the holes of the board at a predetermined depth without damaging the strip or the areas surrounding the holes.
    Type: Grant
    Filed: February 1, 1984
    Date of Patent: March 25, 1986
    Assignee: Honeywell Information Systems Inc.
    Inventor: Thomas A. Morgan
  • Patent number: 4575792
    Abstract: The circuits of a cache unit constructed from a single board are divided into a cache memory section and a controller section. The cache unit is connectable to the central processing unit (CPU) of a data processing system through the interface circuits of the controller section. Test mode logic circuits included within the cache memory section enable cache memories to be tested without controller interference utilizing the same controller interface circuits.
    Type: Grant
    Filed: March 31, 1982
    Date of Patent: March 11, 1986
    Assignee: Honeywell Information Systems Inc.
    Inventor: James W. Keeley
  • Patent number: 4575033
    Abstract: Disclosed is a tilt-swivel base for a CRT display terminal. The base allows the CRT terminal to be readily swiveled around a vertical axis and tilted forward or backward around a horizontal axis or positioned with a combination of both movements. The cradle of the base may be placed within a recess formed in a horizontal supporting surface and thereby confine the base within the recess. By having the recess front-to-back width approximately equal to the front-to-back width of the cradle and the side to side length greater than the side to side width of the cradle, the CRT display terminal and base can be moved from side to side within the recess while still confining it to a fixed front-to-back position. By providing the cradle with a convex front surface and a triangular back surface, the base and CRT display terminal may be swiveled up to the point that one of the two angled back edges of the cradle comes into full contact with the back edge of the recess.
    Type: Grant
    Filed: April 4, 1983
    Date of Patent: March 11, 1986
    Assignee: Honeywell Information Systems Inc.
    Inventors: Helmut H. Henneberg, Richard R. Dillon, Domenic R. Romano, Roger L. Hall
  • Patent number: 4575795
    Abstract: The present invention relates to digital logic circuitry for detecting a predetermined character of a data string for operand data stored in a temporary storage memory or while the data is being loaded into the temporary storage memory, wherein the data string length and the starting location of temporary storage memory in which the data string is to be stored is variable. A first comparator element compares a write address pointer to a start address pointer and an adder generates a sign pointer which indicates an address of temporary storage memory of the predetermined character. A second comparator element utilizes the pointers and the resultant outputs of the first comparator and the adder to indicate the end of the data string.
    Type: Grant
    Filed: April 1, 1983
    Date of Patent: March 11, 1986
    Assignee: Honeywell Information Systems Inc.
    Inventors: Donald C. Boothroyd, Robert W. Norman, Jr.
  • Patent number: 4575774
    Abstract: A track on a disk surface of a disk drive is formatted in sectors, each sector having an address portion and a data portion. The disk drive generates a byte clock signal which increments a counter. The counter output signals address a read only memory which generates signals to control the address comparison in the address portion and the reading or writing of data bytes in the data portion of the sector.
    Type: Grant
    Filed: June 22, 1984
    Date of Patent: March 11, 1986
    Assignee: Honeywell Information Systems Inc.
    Inventors: Bruce H. Tarbox, Donald J. Rathbun, Taian Su
  • Patent number: 4573116
    Abstract: An improved multiword data register array which features RAM technology to provide a greater memory capacity in a smaller space than a conventional register arrays. Whereas RAM technology does not ordinarily include the capability of simultaneously reading and writing, in accordance with the present invention, data may be written into the register on a first half cycle of a clock signal and read out of memory on the second half cycle of the same clock signal. If the writing and the reading of the data relate to the same address in the register array, the data may be read directly from the input circuit.
    Type: Grant
    Filed: December 20, 1983
    Date of Patent: February 25, 1986
    Assignee: Honeywell Information Systems Inc.
    Inventors: Richard H. Ong, Peter C. Economopoulos, Russell W. Guenthner
  • Patent number: 4571072
    Abstract: A computer aided design (CAD) system is operative to generate an output containing only the additions and deletions to an existing master artwork. The CAD output is in turn applied to photoplotter equipment which produces a "delete" artwork containing line representations of only the etch/wires to be deleted from the original master artwork and an "add" artwork containing line representations of ony the etch/wires to be added to the same original master artwork. These two artworks are photographically combined with the original master artwork in a predetermined manner to produce a new PWB artwork which incorporates the added and deleted wire changes.
    Type: Grant
    Filed: September 30, 1983
    Date of Patent: February 18, 1986
    Assignee: Honeywell Information Systems Inc.
    Inventors: Arthur J. Bourbeau, Jr., John P. Doherty
  • Patent number: 4569009
    Abstract: A power supply for providing a selectable predetermined regulated output voltage. A switching regulator circuit provides the conversion of an input voltage to a DC output voltage and a control circuit, which senses the output voltage, controls the conversion of the switching regulator circuit. In the present invention, an amplifier, having selectable gain values, is interposed in the feedback loop, i.e., between the output terminal of the power supply and the control circuit. Thus a predetermined portion of the output voltage is fed back to the control circuit, thereby selectively determining the output voltage without necessitating changes to the switching regulator circuit or the control circuit.
    Type: Grant
    Filed: March 5, 1984
    Date of Patent: February 4, 1986
    Assignee: Honeywell Information Systems Inc.
    Inventor: Luther L. Genuit
  • Patent number: 4567571
    Abstract: In a computer system, there is included a memory unit which includes a volatile memory store, and a memory control circuit connected with the memory unit thereby permitting the computer system to be operated in a step mode, the memory control circuit comprising a step clock generator which generates a gated clock signal. A register element receives a step command signal, an indication from the computer system that the memory unit is to be operated in the step mode, and generates the step mode control signal in response to said step command signal. A shift register receives a strobe command signal from the computer system indicating a request for a memory cycle, and delays the strobe command signal, each stage of the shift register representing a successive step when the computer system is operated in the step mode.
    Type: Grant
    Filed: February 15, 1985
    Date of Patent: January 28, 1986
    Assignee: Honeywell Information Systems, Inc.
    Inventor: Richard C. Moffett
  • Patent number: 4567593
    Abstract: A specialized circuit set is included in a data processing system wherein the circuit set registers can be configured into a serial array. A clock signal distribution system delivers controlled clock signals to selected serial arrays. A maintenance data processor provides predetermined signal groups and addressing apparatus responsive to the predetermined signal groups loads and unloads register arrays in response to the predetermined signals. A predetermined signal group is entered into the serial register array, a predetermined number of clock cycles are applied, and the resulting signals shifted from the serial register array are applied to the maintenance data processor for display or analysis. By comparing the expected result for a given initial state with the actual result of an operation sequence, the accuracy of the operation of the data processing system, or any portion thereof, is thereby determined.
    Type: Grant
    Filed: October 6, 1983
    Date of Patent: January 28, 1986
    Assignee: Honeywell Information Systems Inc.
    Inventor: Lawrence D. Bashaw
  • Patent number: 4563736
    Abstract: A single computer board data processing system includes a multiport memory system which is accessible by I/O controllers through a system bus I/O memory port or directly by the system's central processing unit (CPU) via a CPU memory port. The logic and control circuits of the memory ports and CPU are included within the computer main board while memory modules/pacs are contained on one or more memory daughter boards which plug into memory input/output connectors contained on the main board. The port address and data paths connect in common to the memory connectors for transmitting and receiving memory addresses and data between the memory modules and the CPU and I/O ports. At least one register connects between the CPU and to common address path.
    Type: Grant
    Filed: June 29, 1983
    Date of Patent: January 7, 1986
    Assignee: Honeywell Information Systems Inc.
    Inventors: Daniel A. Boudreau, Edward R. Salas, Richard C. Zelley
  • Patent number: 4562536
    Abstract: A multilevel set associative cache system whose directory and cache store organized into levels of memory locations. Round robin replacement apparatus is used to identify in which level information is to be replaced. The directory includes error checking apparatus for generating address check bits which are written into directory locations together with addresses. Control apparatus in response to error signals from the error checking apparatus degrades cache operation to those levels detected to be free from errors. Test error mode control apparatus which couples to the replacement and check bit apparatuses causes the address check bits to be selectively forced to incorrect values in response to commands received from a central processing unit enabling the verification of both the checking and control apparatus without interference from other operations initiated by the central processing unit.
    Type: Grant
    Filed: June 30, 1983
    Date of Patent: December 31, 1985
    Assignee: Honeywell Information Systems Inc.
    Inventors: James W. Keeley, Robert V. Ledoux, Virendra S. Negi
  • Patent number: 4561053
    Abstract: In an input/output multiplexer of a data processing unit, a plurality of components, capable of independent activity, provide for the simultaneous execution of a multiplicity of operations involving the exchange of signal groups between a central subsystem and peripheral subsystems. The input/output multiplexer includes apparatus for controlling the receipt from delivery to the central subsystem and peripheral subsystems of signal groups. Apparatus is provided to execute address development normally performed in the central subsystem. Apparatus is also provided to analyze control subsystem signal groups and generate pre-selected command signal groups for delivery to the central subsystem or to the peripheral subsystems. Apparatus in the input/output multiplexer also provides a status of each operation currently in execution.
    Type: Grant
    Filed: December 12, 1983
    Date of Patent: December 24, 1985
    Assignee: Honeywell Information Systems Inc.
    Inventor: Knute S. Crawford
  • Patent number: 4559595
    Abstract: In a data processing system, a bus is provided for the transfer of information between units coupled to the bus. The units are coupled in a priority arrangement which is distributed thereby providing priority logic in each of the units and allowing bus transfer cycles to be generated in an asynchronous manner. Priority is normally granted on the basis of physical position on the bus, highest priority being given to the first unit on the bus and lowest priority being given to the last unit on the bus. Each of the units includes priority logic which includes logic elements for requesting a bus cycle, such request being granted if no other higher priority unit has also requested a bus cycle. The request for and an indication of the grant of the bus cycle are stored in each unit so requesting and being granted the bus cycle respectively, only one such unit being capable of having the grant of a bus cycle at any given time, whereas any number of such units may have its request pending at any particular time.
    Type: Grant
    Filed: December 27, 1982
    Date of Patent: December 17, 1985
    Assignee: Honeywell Information Systems Inc.
    Inventors: Daniel A. Boudreau, Edward R. Salas, James M. Sandini
  • Patent number: 4558839
    Abstract: A mounting bracket system mounts a factory data collection terminal vertically to a wall to secure the terminal rigidly to the wall surface and also to permit a quick disconnect of the terminal. This is accomplished by fastening two brackets with keyhole slots which are attached to the upper area of the terminal and using two spring loaded captive fasteners which are accessible from the front of the terminal and attached to the bottom of the terminal.
    Type: Grant
    Filed: May 23, 1985
    Date of Patent: December 17, 1985
    Assignee: Honeywell Information Systems Inc.
    Inventors: Jay Kaplan, Ray Marchant
  • Patent number: 4558412
    Abstract: In a terminal system comprising a central processor subsystem, a memory subsystem and a plurality of peripheral subsystems, all connected in common to a system bus, the system bus timing is divided into a plurality of fixed times including a central processor (CPU) bus cycle and a plurality of Direct Memory Access (DMA) bus cycles. The central processor subsystem communicates with the memory subsystem during CPU bus cycles and the peripheral subsystems communicate with the memory subsystem on DMA bus cycles.Particular peripheral subsystems are assigned to particular DMA channels. These DMA channels communicate with the memory subsystem on particular DMA bus cycles which are operative in a revolving priority, with the first DMA bus cycle occuring after the last DMA bus cycle of the previous sequence of DMA bus cycles.A plurality of peripheral subsystems are wired to a particular DMA channel in a daisy chain fashion with the peripheral subsystem wired closest to the system bus having top priority.
    Type: Grant
    Filed: December 1, 1983
    Date of Patent: December 10, 1985
    Assignee: Honeywell Information Systems Inc.
    Inventors: Minoru Inoshita, Gerald N. Winfrey
  • Patent number: 4558429
    Abstract: A data processing system includes a plurality of memory command generating units which connect to a common bus network with a number of memory subsystems. Each subsystem includes a controller which controls the operation of a number of memory module units and includes a number of queue circuits for storing memory requests to be processed. The memory controller further includes control apparatus connected to monitor bus activity. In response to certain bus activity conditions occurring during multiword transfer operations, the control apparatus operates to lengthen the time between successive multiword transfers of data to the bus so as to ensure that new requestors having lower priorities than a memory controller gain access to an available queue notwithstanding the amount of bus delay incurred in transmitting their memory requests.
    Type: Grant
    Filed: December 17, 1981
    Date of Patent: December 10, 1985
    Assignee: Honeywell Information Systems Inc.
    Inventors: George J. Barlow, Chester M. Nibby, Jr., Robert B. Johnson