Patents Assigned to Hynix Semiconductor
  • Method for operating semiconductor memory device
    Patent number: 8514633
    Abstract: A method for operating a semiconductor memory device includes the steps of: erasing memory cells of a memory block to set the memory cells in a first erased state, programming a part of the memory cells of the memory block to convert them into a programmed state, raising threshold voltages of selected memory cells of the memory block and converting the selected memory cells from the programmed state to a second erased state, and reading data from the memory cells in the first erased state, the programmed state, and the second erased state, and outputting the data read from the memory cells in the first and second erased states with the same value.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: August 20, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Byoung Kwan Jeong
  • Semiconductor memory device and method for operating the same
    Patent number: 8514639
    Abstract: A semiconductor memory device includes a plurality of banks, a clock input unit configured to receive an external data clock, an internal data clock generation unit configured to receive the external data clock from the clock input unit and generate an internal data clock by delaying the external data clock by a delay amount which changes in correspondence to the number of banks activated among the plurality of banks, and a data buffer unit configured to buffer a data signal in response to the internal data clock.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: August 20, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kwang-Jin Na
  • System including semiconductor devices and controller and method for operating the same
    Patent number: 8511564
    Abstract: A semiconductor device includes a device identification detection code output block configured to output a device identification detection code to an outside of the semiconductor device when the semiconductor device enters an identification (ID) read mode, a code comparison block configured to compare a device selection code applied from the outside with the device identification detection code when the semiconductor device enters a device selection mode, and generate a device matching signal based on a comparison result, and an internal circuit block configured to decide whether to perform a predetermined internal operation based on the device matching signal when the semiconductor device enters an operation control mode.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: August 20, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jung-Taek You
  • Non-volatile memory device and method for fabricating the same
    Patent number: 8513076
    Abstract: A non-volatile memory device includes a peripheral circuit region and a cell region. A method for fabricating the non-volatile memory device includes forming gate patterns over a substrate, the gate pattern including a tunnel insulation layer, a floating gate electrode, a charge blocking layer and a control gate electrode, and removing the control gate electrode and the charge blocking layer of the gate pattern formed in the peripheral circuit region.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: August 20, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Nam-Jae Lee
  • Method for fabricating metal pattern in semiconductor device
    Patent number: 8513132
    Abstract: A method for fabricating a metal pattern in a semiconductor device includes forming a metal layer over a substrate, forming a hard mask layer over the metal layer, forming a sacrifice pattern over the hard mask layer, forming a spacer pattern on sidewalks of the sacrifice pattern, removing the sacrifice pattern, forming a hard mask pattern by etching the hard mask layer using the spacer pattern as an etch barrier, forming an etching protection layer over the hard mask pattern and on sidewalks of the hard mask pattern, and forming the metal pattern by performing primary and secondary etching processes on the metal layer using the etching protection layer as an etch barrier.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: August 20, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Mi-Na Ku
  • Delay-locked loop having a loop bandwidth dependency on phase error
    Patent number: 8513991
    Abstract: Circuits, methods, and apparatus that vary one or more attributes or parameters of a closed-loop clock circuit as a function of a characteristic of its phase error. One example provides a delay-locked loop having a loop bandwidth that can be varied as a function of its phase error. In this specific example, current phase error is determined. This determination may be made directly, either by measuring phase error, or indirectly, by determining if phase error is within one or more ranges of values. Once the phase error is determined, the loop bandwidth can be set. In one example, the loop bandwidth is set by adjusting the depth, type, or depth and type of the delay-locked loop's loop filter. In this way, large phase errors can be reduced quickly by increasing loop bandwidth, while small phase errors can be used to decrease loop bandwidth, thereby improving jitter performance.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: August 20, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Youn-Cheul Kim
  • Method for fabricating an electrostatic discharge protection device
    Patent number: 8513082
    Abstract: An electrostatic discharge protection device includes a substrate where an active region is defined by an isolation layer, a gate electrode simultaneously crossing both the isolation layer and the active region, and a junction region formed in the active region at both sides of the gate electrode and separated from the isolation layer by a certain distance in a direction where the gate electrode is extended. The electrostatic discharge protection device is able to prevent the increase of a leakage current while securing an electrostatic discharge protection property that a semiconductor device requires.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: August 20, 2013
    Assignee: Hynix Semiconductor inc.
    Inventors: Jang-Hoo Kim, Ho-Woung Kim
  • Semiconductor device with vertical gate and method for manufacturing the same
    Patent number: 8507374
    Abstract: A semiconductor device and a method for manufacturing the same are disclosed. The method for manufacturing the semiconductor device comprises: forming a plurality of first pillar patterns each of which includes a sidewall contact by selectively etching a semiconductor substrate; forming a buried bit line at a lower portion of a region between two neighboring first pillar patterns; forming a plurality of second pillar patterns by selectively etching upper portions of the first pillar patterns; and forming a gate coupling second pillar patterns arranged in a direction crossing the bit line, the gate enclosing the second pillar patterns.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: August 13, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung Hwan Kim
  • Semiconductor device with buried bit lines and method for fabricating the same
    Patent number: 8507342
    Abstract: A semiconductor device includes active regions separated by a trench, a separation layer dividing the trench, and buried bit lines buried in the trench with the separation layer interposed between the buried bit lines.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: August 13, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Ki-Ro Hong
  • Non-volatile memory device and method for fabricating the same
    Patent number: 8507973
    Abstract: A non-volatile memory device includes a channel that extends from a substrate in a vertical direction and includes a first portion including an impurity doped region and a second portion disposed under the first portion; and a plurality of memory cells and a selection transistor that are stacked over the substrate along the channel, where the impurity doped region includes a second impurity doped region that forms a side surface and an upper surface of the first portion and a first impurity doped region that covers the second impurity doped region, and a bandgap energy of the second impurity doped region is lower than a bandgap energy of the first impurity doped region.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: August 13, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Byung-In Lee
  • Semiconductor device, method for operating the same, and memory system including the same
    Patent number: 8508263
    Abstract: A semiconductor device includes a clock supply circuit configured to generate an internal clock by using an external clock, an internal circuit configured to operate in synchronization with the internal clock and enter a power-down mode in response to a power-down signal, and a controller configured to control an entry of the clock supply circuit into the power-down mode in response to a locking signal, which represents that the clock supply circuit has been locked, and the power-down signal.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: August 13, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Nak-Kyu Park
  • Semiconductor device employing fin-type gate and method for manufacturing the same
    Patent number: 8507349
    Abstract: A semiconductor device comprises an active region having an upper portion and a sidewall portion which are protruded from the top surface of a device isolation region, and a silicide film disposed in the upper portion and the sidewall portion of the active region, thereby effectively reducing resistance in a source/drain region of the semiconductor device. As a result, the entire resistance of the semiconductor device comprising a fin-type gate can be reduced to improve characteristics of the semiconductor device.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: August 13, 2013
    Assignee: Hynix Semiconductor Inc
    Inventor: Seung Hyun Lee
  • Phase-change memory device and method of fabricating the same
    Patent number: 8508021
    Abstract: A phase-change memory device with improved deposition characteristic and a method of fabricating the same are provided. The phase-change memory device includes a semiconductor substrate having a phase-change area, a first material-rich first phase-change layer forming an inner surface of the phase-change area and comprised of a hetero compound of the first material and a second material, and a second phase-change layer formed on a surface of the first phase-change layer to fill the phase-change area.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: August 13, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Keun Lee, Jin Hyock Kim, Young Seok Kwon
  • Apparatus and method for outputting data of semiconductor memory apparatus
    Patent number: 8508273
    Abstract: An apparatus for outputting data of a semiconductor memory apparatus, which is capable of varying the slew rate and the data output timing, includes a bias generator that generates a bias having a level corresponding to a set value, a slew rate controller that controls a pull-up slew rate or a pull-down slew rate of input data on the basis of the bias generated by the bias generator, and a data outputting unit that outputs data on the basis of the slew rate controlled by the slew rate controller. Therefore, it is possible to satisfy various operational conditions without changing the structure of the circuit and to correspond rapidly and appropriately whit a change in the system, which enables the applied range of the products to be extended.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: August 13, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Dong-Uk Lee
  • Template derivative for forming ultra-low dielectric layer and method of forming ultra-low dielectric layer using the same
    Patent number: 8507665
    Abstract: A reactive cyclodextrin derivative or a reactive glucose derivative is used as a template derivative for forming an ultra-low dielectric layer. A layer is formed of the reactive cyclodextrin derivative or the reactive glucose derivative capped with Si—H and then cured in an atmosphere of hydrogen peroxide to form the ultra-low dielectric layer.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: August 13, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sung Kyu Min, Ja Chun Ku, Sang Tae Ahn, Chai O Chung, Hyeon Ju An, Hyo Seok Lee, Eun Jeong Kim, Chan Bae Kim
  • Semiconductor device having a buried gate and method for manufacturing the same
    Patent number: 8507344
    Abstract: A semiconductor device and a method for manufacturing the same are disclosed. The method for forming the semiconductor device includes forming one or more buried gates in a semiconductor substrate, forming a landing plug between the buried gates, forming a bit line region exposing the landing plug over the semiconductor substrate, forming a glue layer in the bit line region, forming a bit line material in the bit line region, and removing the glue layer formed at inner sidewalls of the bit line region, and burying an insulation material in a part where the glue layer is removed. A titanium nitride (TiN) film formed at sidewalls of the damascene bit line is removed, so that resistance of the bit line is maintained and parasitic capacitance of the bit line is reduced, resulting in the improvement of device characteristics.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: August 13, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Chan Woo Kim
  • Semiconductor integrated circuit having fuse circuit and driving method of fuse circuit
    Patent number: 8508284
    Abstract: A semiconductor integrated circuit includes a fuse connected between a first node and a second node, a first driver configured to pull down a voltage of the first node in an initialization period in response to a fuse sensing signal, a second driver configured to pull up a voltage of the second node in an initial period of a fuse sensing period in response to the fuse sensing signal, a sensor configured to determine whether the fuse is blown or not in response to a voltage of the first node, and a third driver configured to drive the second node to a voltage level lower than a pull-up voltage level of the second driver after the initial period of the fuse sensing period in response to an output signal of the sensor and the fuse sensing signal.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: August 13, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Young-Han Jeong
  • Voltage generation circuit and nonvolatile memory device including the same
    Patent number: 8509019
    Abstract: A voltage generation circuit for providing a read or verification voltage of a nonvolatile memory device includes a first voltage generation unit configured to output a first voltage using a first reference voltage, a bouncing compensation unit configured to change the first voltage using a first control signal, the first voltage, and a voltage of a global source line when a read or verification operation is performed on the nonvolatile memory device, and to output a changed first voltage as a second voltage, a second reference voltage generation unit configured to generate a second reference voltage, and an amplification unit configured to amplify a difference between the second voltage and the second reference voltage according to a set resistance ratio and to output a result of the amplification as a third voltage.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: August 13, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Yu Jong Noh
  • Data output circuit and data output method thereof
    Patent number: 8508272
    Abstract: A data output circuit and a data output method thereof are provided. The data output circuit includes a delay locked loop, a duty ratio correction block, and an output unit. The delay locked loop corrects a duty ratio of a first internal clock. The delay locked loop includes a correction enable signal output unit configured to output a correction enable signal when the operation of correcting the duty ratio of the first internal clock is completed. The duty ratio correction block corrects the duty ratio of the first internal clock by using a duty ratio detection signal in response to the correction enable signal, and outputs the corrected first internal clock as an output clock. The output unit detects a duty ratio of the output clock, generates the duty ratio detection signal to the duty ratio correction block, and outputs a data strobe signal in response to the output clock.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: August 13, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jin-Il Chung
  • Semiconductor memory device, method of testing the same and system of testing the same
    Patent number: 8503260
    Abstract: A method of testing a semiconductor memory device comprises receiving a clock, addresses, commands, and data from a test device through channels, generating an internal bank address in response to the addresses and the commands, performing a multi-bit parallel test for each of a plurality of banks based on the addresses, the commands, the data, and the internal bank address, and providing the test device with a test result signal.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: August 6, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jeong-Tae Hwang, Jeong-Hun Lee