Patents Assigned to Hynix Semiconductor
  • Method for Forming Fine Patterns of Semiconductor Device
    Publication number: 20130252174
    Abstract: A method for forming fine patterns of a semiconductor device employs a double patterning characteristic using a mask for forming a first pattern including a line pattern and a mask for separating the line pattern, and a reflow characteristic of a photoresist pattern.
    Type: Application
    Filed: May 15, 2013
    Publication date: September 26, 2013
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Jae Seung Choi
  • Schottky diode, resistive memory device having schottky diode and method of manufacturing the same
    Patent number: 8541775
    Abstract: A schottky diode, a resistive memory device including the schottky diode and a method of manufacturing the same. The resistive memory device includes a semiconductor substrate including a word line, a schottky diode formed on the word line, and a storage layer formed on the schottky diode. The schottky diode includes a first semiconductor layer, a conductive layer formed on the first semiconductor layer and having a lower work function than the first semiconductor layer, and a second semiconductor layer formed on the to conductive layer.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: September 24, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Seung Beom Baek, Young Ho Lee, Jin Ku Lee, Mi Ri Lee
  • Semiconductor memory device and thermal code output circuit capable of correctly measuring thermal codes
    Patent number: 8542548
    Abstract: A thermal code output circuit is provided, comprising a pulse signal generator configured to receive multiple period signals and generate a pulse signal in response to a test mode signal, a thermal code output unit configured to output multiple thermal codes in response to the pulse signal, and a strobing signal output unit configured to output the pulse signal or a reference voltage selectively as a strobing signal in response to the test mode signal.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: September 24, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sun Mo An
  • Semiconductor integrated circuit and method for driving the same
    Patent number: 8542044
    Abstract: A semiconductor integrated circuit includes: a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a source clock signal by a first delay time for obtaining a lock, wherein an update period of the DLL is controlled in response to an update period control signal after locking is completed; and an update period controller configured to generate the update period control signal based on a second delay time occurring in a loop path of the DLL in response to the source clock signal and a plurality of control signals provided from the DLL.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: September 24, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yong-Ju Kim, Dae-Han Kwon, Hae-Rang Choi, Jae-Min Jang
  • Method for Fabricating a Semiconductor Device Having a Saddle Fin Transistor
    Publication number: 20130244413
    Abstract: A method for fabricating a semiconductor device includes forming a pad nitride layer that exposes an isolation region over a cell region of a semiconductor substrate; forming a trench in the isolation region of the semiconductor substrate; forming an isolation layer within the trench; etching an active region of the semiconductor substrate by a certain depth to form a recessed isolation region; etching the isolation layer by a certain depth to form a recessed isolation region; depositing a gate metal layer in the recessed active region and the recessed isolation region to form a gate of a cell transistor; forming an insulation layer over an upper portion of the gate; removing the pad nitride layer to expose a region of the semiconductor substrate to be formed with a contact plug; and depositing a conductive layer in the region of the semiconductor substrate to form a contact plug.
    Type: Application
    Filed: May 2, 2013
    Publication date: September 19, 2013
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Jin Yul Lee, Dong Seok Kim
  • Method of erasing semiconductor memory device
    Patent number: 8537632
    Abstract: A method of erasing a semiconductor memory device comprises grouping a plurality of word lines of each memory block into at least two groups based on intensity of disturbance between neighboring word lines; performing an erase operation by applying a ground voltage to all word lines of a selected memory block and by applying an erase voltage to a well of the selected memory block; and first increasing the ground voltage of one group of the groups to a positive voltage during the erase operation.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: September 17, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hea Jong Yang, Hee Youl Lee, Sung Jae Chung, Hyun Heo, Jeong Hyong Yi, Yong Dae Park
  • Semiconductor memory device and method of operating the same
    Patent number: 8537624
    Abstract: A semiconductor memory device that may perform a second operation during a first operation comprises a command decoder for generating a decoded command signal, a suspend pulse and a resume pulse, and a storage unit for storing the decoded address signal, the decoded command signal and a data signal in response to the suspend pulse and providing the decoded address signal, the decoded command signal and the decoded data signal as a stored address signal, a stored command signal and a stored data signal, respectively, in response to the resume pulse.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: September 17, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Ji-Hyae Bae
  • Method for fabricating pellicle of EUV mask
    Patent number: 8535545
    Abstract: A method for fabricating a pellicle of an EUV mask is provided. An insulation layer is formed over a silicon substrate, and a mesh is formed over the insulation layer. A frame exposing a rear surface of the insulation layer is formed by selectively removing a center portion of a rear surface of the silicon substrate. A membrane layer is deposited over the mesh and an exposed top surface of the insulation layer which is adjacent to the mesh. A rear surface of the membrane layer is exposed by selectively removing the portion of the insulation layer which is exposed by the frame.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: September 17, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Yong Dae Kim
  • Nonvolatile memory device and method for operating the same
    Patent number: 8537616
    Abstract: A nonvolatile memory device includes a plurality of memory blocks and a high voltage application unit configured to apply a high voltage to a word line of a memory block unselected from among the plurality of memory blocks and float the word line, during the erase operation.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: September 17, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Nam-Kyeong Kim
  • Semiconductor device having control bitline to prevent floating body effect
    Patent number: 8537631
    Abstract: A vertical semiconductor device is provided. The semiconductor device includes a cell array including a control bit line connected to cells and electrically isolated from a bit line, and a floating body control circuit for applying a floating control voltage to the control bit line in a predetermined period.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: September 17, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Woo Young Chung
  • Semiconductor memory device
    Patent number: 8531892
    Abstract: A semiconductor memory device is disclosed. The semiconductor memory device converts a sequentially-changing step voltage into a current so as to provide a write current, and minimizes the influence of a threshold voltage variation caused by fabrication deviation, such that it can be stably operated. The semiconductor memory device includes a current driver. The current driver includes a step voltage provider configured to provide a step control voltage sequentially changing in response to a pulse control signal, a control current provider configured to provide a control current in response to the step control voltage, and a write driver configured to provide a write current capable of writing data in a memory cell in response to the control current.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: September 10, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Tae Hun Yoon
  • Printed circuit board having adaptable wiring lines and method for manufacturing the same
    Patent number: 8530754
    Abstract: A printed circuit board having adaptable wiring lines includes an insulation layer. Electrode terminals and ball lands are formed on an upper surface of the insulation layer and are separated from each other. Wiring patterns are formed on the insulation layer, interposed between the electrode terminals and the ball lands, and partially removed in a region between the electrode terminals and the ball lands. Conductive members are selectively formed in the regions where the wiring patterns are partially removed to selectively connect the electrode terminals and the ball lands.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: September 10, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Shin Young Park
  • Semiconductor device
    Patent number: 8531211
    Abstract: A semiconductor device includes a first signal delay block configured to delay a first edge of an input signal with varying delay amounts, maintain a second edge of the input signal, and output at least one first driving signal, a second signal delay block configured to delay the second edge of the input signal with the varying delay amounts, maintain the first edge of the input signal, and output at least one second driving signal, and an output pad driving block configured to drive a data output pad with a first voltage in response to the first driving signal and drive the data output pad with a second voltage in response to the second driving signal.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: September 10, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jae-Heung Kim
  • Delay control circuit and semiconductor memory device including the same
    Patent number: 8531897
    Abstract: A delay control circuit includes a delay locked loop configured to delay an external clock by a first delay amount and generate an internal clock, a first delay unit configured to delay an input signal by a first delay amount, a first replica delay unit having a replica delay amount corresponding to a modeled delay amount of a system, a delay control unit configured to control the replica delay amount in response to a latency of an input signal, a measurement unit configured to measure the first delay amount and the controlled replica delay amount and generate path information, an operation unit configured to generate delay information in response to the latency of the input signal and the path information, and a latency delay unit configured to delay the delayed input signal of the first delay unit by the delay information and generate a latency signal.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: September 10, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kyung-Whan Kim
  • Semiconductor device for performing test operation and method thereof
    Patent number: 8531200
    Abstract: A semiconductor device includes an internal operation signal generation circuit configured to generate an internal operation signal in response to a signal applied through a reset signal input pad during a test period.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: September 10, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sun-Suk Yang
  • Current control circuit
    Patent number: 8531895
    Abstract: A current control device is disclosed, which reduces a standby current of a semiconductor memory device and a turn-on current of a transistor. The current control device includes an input controller configured to combine a trigger signal and a set signal controlling a circuit operation status, and a drive unit configured to drive an output signal of the input controller, wherein the drive unit includes a current controller for selectively providing a ground voltage in response to an activation status of a pull-down driving signal.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: September 10, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Woo Seok Song
  • Transistor of semiconductor device and method for manufacturing the same
    Patent number: 8530962
    Abstract: Provided are a transistor of a semiconductor device and a method for manufacturing the same. A gate induced drain leakage (GIDL) current is reduced by decreasing a work function at an upper portion of a gate electrode, and a threshold voltage of the transistor is maintained by maintaining a work function at a lower portion of the gate electrode at a high level, thereby reducing a leakage current of the transistor and reducing a read time and a write time of the semiconductor device. The transistor of the semiconductor device includes: a recess with a predetermined depth in a semiconductor substrate; a first gate electrode disposed within the recess; and a second gate electrode disposed on the first gate electrode into which ions of one or more of nitrogen (N), oxygen (O), arsenic (As), aluminum (Al), and hydrogen (H) are doped.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: September 10, 2013
    Assignee: Hynix Semiconductor Inc
    Inventor: Kyoung Chul Jang
  • Semiconductor memory device having low power consumption type column decoder and read operation method thereof
    Patent number: 8531894
    Abstract: The present invention relates to a semiconductor memory device having a low power consumption type column decoder and read operation method thereof. In accordance with the semiconductor memory device and read operation method thereof according to the present invention, one of a plurality of decoding units of a column decoder is selectively operated according to a logic value(s) of one of some of bits of a column address signal. It is thus possible to reduce unnecessary switching current.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: September 10, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Yong Deok Cho
  • Method for manufacturing a semiconductor device capable of preventing the decrease of the width of an active region
    Patent number: 8530330
    Abstract: A method for manufacturing a semiconductor device that can prevent the loss of an isolation structure and that can also stably form epi-silicon layers is described. The method for manufacturing a semiconductor device includes defining trenches in a semiconductor substrate having active regions and isolation regions. The trenches are partially filled with a first insulation layer. An etch protection layer is formed on the surfaces of the trenches that are filled with the first insulation layer. A second insulation layer is filled in the trenches formed with the etch protection layer to form an isolation structure in the isolation regions of the semiconductor substrate. Finally, portions of the active regions of the semiconductor substrate are recessed such that the isolation structure has a height higher than the active regions of the semiconductor substrate.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: September 10, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sang Tae Ahn, Ja Chun Ku, Eun Jeong Kim, Wan Soo Kim
  • Non-volatile memory device and method for fabricating the same
    Patent number: 8530956
    Abstract: A non-volatile memory device including a memory string including a plurality of memory cells coupled in series. The non-volatile memory device includes the memory string including a first semiconductor layer and a second conductive layer with a memory gate insulation layer therebetween, a first selection transistor comprising a second semiconductor layer coupled with one end of the first semiconductor layer, a second selection transistor comprising a third semiconductor layer coupled with the other end of the first semiconductor layer, and a fourth semiconductor layer contacting the first semiconductor layer in a region where the second conductive layer is not disposed.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: September 10, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang-Bum Lee