Abstract: A ferroelectric memory device, e.g., nonvolatile, has an effective layout by eliminating a separate cell plate line. The ferroelectric memory device includes first and second split word lines formed over first and second active regions of a semiconductor substrate, and the first and second active regions are isolated from each other. Source and drain regions are formed in the first active region on both sides of the first split word line and the second active region on both sides of the second split word line. A conductive barrier layer, a first capacitor electrode and a ferroelectric layer are sequentially formed on the first and second split word lines. Two second capacitor electrodes with one connected to one of the source and drain regions of the second active region is formed over the first split word line. The other one is connected to one of the source and drain regions of the first active region and is formed over the second split word line.

Abstract: A capacitor and a method of manufacturing the same are disclosed. The BST dielectric film is disposed between the lower electrode by coating a sidewall of the upper electrode and then forming the lower electrode in a second contact hole defined by the upper electrode and BST film. As such, degradation in the step coverage characteristic caused by forming a BST dielectric film having a desired composition ratio is avoided.

Abstract: A bi-directional high-voltage RESURF EDMOS (REduced SURface Extended Drain MOS) transistor which can endure a high voltage at its source by providing drift regions at both sides, i.e., the source and drain of the conventional RESURF LDMOS (Lateral DMOS) transistor, and exchanging the drain and the source when an analog signal of high voltage is inputted. Further, the bi-directional high-voltage RESURF EDMOS transistor provides a high-voltage analog multiplexer circuit employing a RESURF EDMOS transistor which is capable of reducing the number of necessary high-voltage elements and performing a stable operation, by constructing a high-voltage analog multiplexer having at least three inputs and a multistage high-voltage multiplexer circuit of push-pull type, pass transistor type, and combined form of push-pull type and pass transistor type by using the bi-directional high-voltage, RESURF EDMOS transistor.

Abstract: There is a vinyl 4-hydroxybenzal-vinylalcohol-vinyl acetate copolymer, a 4-t-butoxycarbonyloxybenzal-vinyl alcohol-vinyl acetate copolymer and a vinyl 4-t-butoxycarbonyloxybenzal-vinyl 4-hydroxybenzal-vinyl alcohol-vinyl acetate copolymer suitable for photoresist and methods for preparing the same. The latter two polymers contain 4-hydroxybenzal groups all or parts of which are protected with t-butoxycarbonyl group. Superior in transparency, thermal stability, mechanical strength, and adhesiveness to silicon wafer, the photoresists prepared from the protected copolymers can enhance the resolution of fine circuit by virtue of low weight loss upon the thermal treatment after exposure.

Abstract: An apparatus and method for reducing a pattern jitter is provided that uses a local symmetry forcing wave signal. Pattern jitter is generated when a timing phase of a symbol signal is recovered. The apparatus can include a demultiplexer receiving a preamble and data signal. A nonlinear operation unit preferably only receives the preamble signal from the demultiplexer, and a locally symmetric wave generator preferably only receives the data signal from the demultiplexer. A buffer memory selects from an output signal of the nonlinear operation unit and an output signal of the locally symmetric wave generator. An input signal controller receives a control signal and outputs an input control signal to control the buffer memory and the demultiplexer. The apparatus and method that reduces pattern jitter is a system with reduced complexity and reduced cost to advantageously embody a very large scale integration VLSI or the like.

Abstract: The present invention provides a method for forming a storage electrode on a semiconductor substrate, and in particular to a storage electrode formation method which can prevent formation of a sharp upper edged cylindrical storage electrode, thereby improving a dielectric property and reliability of a capacitor.

Abstract: The present invention relates to a semiconductor device, and more particularly, to a test pattern for evaluating a process of silicide film formation. The test pattern in accordance with the present invention includes: a silicon substrate having an active region and a field region; a first pattern composed of a cross resistor pattern of a polycide layer formed on the field region; and a second pattern composed of polycide layer and a silicide layer formed on the active region. The second pattern includes: a pair of polycide patterns composed of a first polycide strip and a second polycide strip extended in parallel, being spaced from each other a predetermined interval on an insulating film formed on the active region; and an active silicide strip formed between the first polycide strip and the second polycide strip.

Abstract: An active pixel sensor (APS) with an electronic shutter is provided that performs an auto exposure function so that all pixels have substantially equal photosensitive time by controlling a photo-electric charge that is generated in accordance with light transmitted to a photo-diode. The APS includes a switching unit that throughputs the photo-electric charge for a prescribed time based on an externally inputted shutter control signal, and an electric charge storing unit that stores the photo-electric-charge from the switching unit for the prescribed time. The electric charge storing unit outputs the stored photo-electric charge to an electric charge amplifying and outputting unit based on an externally inputted electric charge resetting signal. The APS provides uniform screen brightness for a display apparatus by allowing all pixels to use a substantially identical photosensitive (e.g., exposure) time.

Abstract: Disclosed is a method and apparatus for searching a human three-dimensional (3D) posture which can rapidly and accurately search a human 3D posture by effectively representing the human 3D posture with a small amount of data. According to the method, a posture database is established by extracting posture descriptors using relation among respective joints of a body, and a feature of a query 3D posture is simultaneously extracted in the same manner. Then, the similarity is calculated by comparing the posture descriptor of the query 3D posture with the posture descriptors of postures in the posture database, and then outputted to search the human 3D posture.

Abstract: The present invention relates to a semiconductor technology and more specifically to a method of fabricating a gate electrode of a semiconductor device, where a re-oxidation process that may cause an abnormal oxidation can be eliminated. In a polysilicon/silicide structure or polysilicon/metal structure of gate electrode, a step of etching side parts of gate electrode is performed without any etch mask after gate patterning. Here, the etch can be made by wet or dry etch using an etchant having high selectivity of polysilicon film to a gate oxide film, so that the damaged gate oxide part during the gate patterning is allowed not to make a role of the gate insulating film itself, thereby eliminating the re-oxidation process.

Abstract: A pixel structure with an electronic shutter function using an active pixel sensor (APS) capable of overcoming a disadvantage of conventional pixel structures using the active pixel sensor that reset the pixels not in pixel units but in line units, and thus an electronic shutter cannot be provided, includes a plurality of pixels arrayed in a lattice pattern, a row selection decoder outputting a row selection signal to each pixel, a first line counter counting a number of lines of the pixels selected by the row selection decoder, a line reset selection decoder outputting a line reset signal to each pixel, a second line counter counting a number of lines of the pixel selected by the line reset selection decoder, a column reset selection decoder outputting a column reset signal to each pixel, a first pixel counter counting a number of the pixels selected by the column reset selection decoder, a pixel reading unit reading the pixels in pixel units, and a second pixel counter counting a number of the pixels which

Abstract: A method of fabricating a semiconductor capacitor is disclosed. An impurity layer is formed on a semiconductor substrate. An interlayer insulating film is disposed on an upper surface of the impurity layer and the semiconductor substrate. A contact hole is selectively etched through the interlayer insulating film to the impurity layer. A conductive plug is formed in the contact hole. A metal film pattern having an irregular surface area is disposed on the conductive plug. A dielectric substance film is located directly on the irregular surface of the metal film pattern. A metal electrode is formed on the dielectric substance film.

Abstract: The present invention provides a polymer that can be used as an anti-refelctive coating (ARC) polymer, an ARC composition comprising the same, methods for producing the same, and methods for using the same. The polymer of the present invention is particularly useful in a submicrolithographic process, for example, using KrF (248 nm), ArF (193 nm), or F2 (157 nm) laser as a light source. The polymer of the present invention comprises a chromophore that is capable of absorbing light at the wavelengths used in a submicrolithographic process. Thus, the ARC of the present invention significantly reduces or prevents back reflection of light and the problem of the CD alteration caused by the diffracted and/or reflected light. The ARC of the present invention also significantly reduces or eliminates the standing wave effect and reflective notching.

Abstract: A radio frequency transmission control apparatus for preventing an oscillation in a wideband wireless local loop terminal has a radio frequency transmitting unit for modulating a baseband transmitting signal to a WLL radio frequency band signal and transmitting the modulated signal via an antenna, and the radio frequency transmitting unit is divided into a radio frequency converting unit and a power amplifier unit in accordance with characteristics of each active element constituting the radio frequency transmitting unit. When a power is supplied to the radio frequency transmitting unit, the power is first supplied to the radio frequency converting unit so as to maintain the same at an operating state. After a predetermined time period has elapsed, the power is supplied to the power amplifier unit.

Abstract: A method of forming wires for semiconductor devices can restrict increase of a wires resistance and a contact resistance of the semiconductor device by forming a plug without generating a void or keyhole, and includes a step of forming an insulation film on lower wires, a step of forming a contact hole on the lower wires by selectively etching the insulation film, a step of performing a precleaning process by using an argon sputtering method until the lower wires at the lower portion of the contact hole are etched at a predetermined depth, a step of forming a plug by depositing a tungsten in the contact hole, and a step of forming upper wires on the plug and the second insulation film. A re-deposition layer consisting of a material of the lower wires is formed at the inner walls of the contact hole in the precleaning process, and thus a whole process is simplified by omitting a step of forming a glue layer or adhesion layer.

Abstract: The claimed invention relates to a semiconductor device and a method of fabricating the semiconductor device. More particularly, the claimed invention relates to a method of fabricating the semiconductor device in which parts of a gate electrode at the ends of a channel are lightly doped compared to the center part of the gate electrode, thereby eliminating a hump on a subthreshold current slope. To achieve the objects of the claimed invention, there is provided a semiconductor device that includes a semiconductor substrate divided into an isolation region and an active region. A gate oxide film is formed on a first upper surface of the active region. A gate electrode is formed on a second upper surface of the gate oxide film, the gate electrode having a first part and a second part. The first part is more lightly doped with impurities than the second part. A channel is formed in an upper end of the active region proximate the gate electrode.

Abstract: A programmable analog-to-digital converter (ADC) for use in a CMOS imaging system, the CMOS imaging system having an array of pixels, and the ADC configured to provide a enhanced conversion resolution for pixels providing a low analog voltage level and a relatively coarser conversion resolution for pixels providing a relatively higher analog voltage level.

Abstract: An image sensor capable of preventing the degradation of pinned photodiodes and the generation of leakage current between neighboring pinned photodiodes is provided. The disclosed image sensor contains a plurality of pixel units, each pixel unit having a photodiode region. The image sensor includes a semiconductor substrate of a first conductivity type; a device isolation layer formed in the semiconductor substrate; a field stop layer formed beneath the device isolation layer; a trench formed in the semiconductor substrate, wherein the trench surrounds the photodiode region; a first doping region of the first conductivity type formed beneath the surface of the semiconductor substrate and beneath the surfaces of the trench; an insulating member filling the trench; and a second doping region of a second conductivity type formed in the semiconductor substrate under the first doping region.

Abstract: Methods are disclosed for erasing a flash memory cell including: (a) a semiconductor substrate, (b) a gate, (c) a source, (d) a drain, (e) a well, the gate including: (1) a tunnel oxide film, (2) a floating gate, (3) a dielectric film and (4) a control gate stacked on the semiconductor substrate. In one of the disclosed methods, a negative bias voltage is applied to the control gate, the source and drain are floated, a positive bias voltage is applied to the well to thereby create a positive bias voltage in the source and the drain, a ground voltage is applied to the well at a first time while maintaining the negative bias voltage a the control gate; and subsequently a ground voltage is applied to the control gate.

Abstract: Disclosed are a capacitor for semiconductor device capable of increasing storage capacitance and preventing leakage current, and method of manufacturing the same. According to the present invention. A lower electrode is formed on a semiconductor substrate. The lower electrode is surface-treated so as to prevent generation of a natural oxide layer. An amorphous TaON layer is, as a dielectric layer, deposited on the upper part of the lower electrode. Afterwards, the amorphous TaON layer is thermal-treated in a range of maintaining its amorphous state. Next, an upper electrode is formed on the upper part of the TaON layer.