Abstract: A method for receiving an external signal in synchronization with rising and falling edges of a data strobe signal to generate two internal signals in synchronization with one of both edges of a main clock in a high speed memory device, includes the steps of receiving the external signal to generate a full-swing level signal, dividing the full-swing level signal into a first signal and a second signal in synchronization with the data strobe signal, wherein the first signal is activated in synchronization with rising edges of the data strobe signal and the second signal is activated in synchronization with falling edges of the data strobe signal, aligning the first signal and the second signal with one of both edges of the data strobe signal, and aligning the aligned first and second signals with one of both edges of a main clock.

Abstract: A method of manufacturing a metal wiring in a semiconductor device is disclosed. The method comprises forming a photosensitive film so that an underlying metal wiring can be exposed, adhering an chemical enhancer only to the underlying metal wiring, depositing a metal layer by CECVD method so that the metal layer is selectively deposited at the portion in which the chemical enhancer is formed, removing the photosensitive film and chemical enhancer, and forming a diffusion barrier layer spacer at the sidewall of the metal layer to form an upper metal wiring. Therefore, the disclosed method can solve poor contact with an underlying metal wiring due to shortage of processional margin in the process of forming an upper metal wiring in a high integration semiconductor device.

Abstract: The semiconductor device includes a semiconductor substrate, an insulating layer on the semiconductor substrate wherein a groove is patterned to a predetermined depth in an upper surface of the insulating layer, a fuse layer at sidewalls and on a bottom of the groove, and a wire connected electrically to the fuse layer.

Abstract: A silicon-on-insulator (SOI) device has a reversed stacked capacitor cell and body contact structure. The SOI device includes a semiconductor layer, an isolation film, a first gate, a first source region, a first drain region, a second gate, a second source region, a second drain region, a capacitor, and first, second and third impurity regions. The semiconductor layer includes a gate surface and another surface. The isolation film is of a trench tpye formed in the gate surface of the semiconductor layer. It has a lower surface at a level between the gate surface and the another surface. The isolation film also defines a first device formation region and a second device formation region. The first gate, first source region and first drain region are formed in the first device formation region. The second gate, second source region and second drain region are formed in the second device formation region.

Abstract: The method of the present invention includes providing a silicon substrate having an impurity region, forming an inter-layer insulating film having a contact hole in the impurity region and forming a titanium film and titanium nitride film in the contact hole. The method of the present invention further includes conducting a heat treatment to cause a reaction between the titanium film and the silicon substrate and forming a tungsten plug on the titanium nitride film in the contact hole. The device of the present invention including the bit lines are made up of a first inter-layer insulating film on the substrate having a first contact hole over the impurity region, a titanium film in the first contact hole, a titanium nitride film on the titanium film, a titanium silicide film on the silicon substrate wherein the titanium silicide film does not include an agglomerate, a tungsten plug on the titanium nitride film in the first contact hole and a circuit element on the first inter-layer insulating film.

Abstract: An improved semiconductor device, and a corresponding fabrication method thereof, are provided that include a ground region defined in a semiconductor substrate. A hole is formed using a known electropolishing system to electropolish a portion of a bottom surface of the substrate which corresponds to the ground region. A metal layer is formed on the bottom surface of the substrate and in the hole. The metal layer serves as ground by being linked with a ground metal line formed on a substrate surface.

Abstract: ESD protection circuit which can minimize fluctuation of a gate voltage with an ESD input voltage, for improving an ESD protection capability, including a first transistor connected to an input pad for discharging an ESD charge, a capacitor and a diode connected to the input pad for applying a gate voltage to a gate of the first transistor to improve a bipolar driving capability of the first transistor, a second transistor for controlling drive of the first transistor when the chip is operative, and a resistor for delaying transmission of an ESD charge to an inner circuit when the ESD charge is received at the input pad.

Abstract: An apparatus and method for retrieving a moving picture using a descriptor of a tree-structured moving picture index. If the user starts a query for the retrieval of information, a decoder sends an in-index highest-order key frame number, in-index edge information and an intra-layer threshold value list of a tree-structured moving picture index descriptor stored therein to a server environment. Then, the server environment reads a key frame number and sends it to the decoder. The decoder sends a feature vector designated by the key frame number to the server environment. Subsequently, the server environment first compares the designated feature vector with a query feature vector and, thereafter, the compared result with a threshold value and retrieval precision desired by the user to determine whether the key frame number is concerned with a query picture. If the key frame number is concerned with the query picture, the server environment transfers the retrieved result to a user environment.

Abstract: The present invention relates to a copolymer resin for a photoresist used in far ultraviolet ray such as KrF or ArF, process for preparation thereof, and photoresist comprising the same resin. The copolymer resin according to the present invention is easily prepared by conventional radical polymerization due to the introduction of mono-methyl cis-5-norbonen-endo-2,3-dicarboxylate unit to a structure of norbornene-maleic anhydride copolymer for photoresist. The resin has high transparency at 193 nm wavelength, provides increased etching resistance and settles the problem of offensive odor occurred in the course of copolymer resin synthesis. Further, as the resin composition can be easily controlled due to the molecular structure, the resin can be manufactured in a large scale.

Abstract: Provided are methods for forming ferroelectric capacitors, which prevent decreasing ferroelectric characteristics due to the reaction of a ferroelectric layer with hydroxyl group induced from a inter-layer insulating film which will be formed and contacted with the ferroelectric layer after the formation of the ferroelectric capacitor. After a ferroelectric film such as Pb(Zr,Ti)O3 (PZT) is formed, a ZrO2 film, which is insulator and excellent in diffusion barrier characteristics, is formed so as to enclose the entire ferroelectric layer in order to prevent the damage generated by the reaction. The characteristics of the ferroelectric capacitor are enhanced by the invention.

Abstract: A semiconductor device includes a semiconductor substrate having a trench in its surface, an insulating film in the trench, a doped conductive layer on the insulating film, a gate insulation film and a gate electrode on the doped conductive layer over the trench, and source and drain impurity regions in the surface of the semiconductor substrate at sides of the gate electrode.

Abstract: The present invention provides compounds represented by formulas 1a and 1b; and photoresist polymers derived from the same.

Abstract: A method for fabricating a conductive line pattern for a semiconductor device including the steps of: forming a gate insulation film on the upper surface of a semiconductor substrate; forming a polysilicon layer on the upper surface of the gate insulation film; forming a WNx film on the upper surface of the polysilicon layer; forming a first insulation film on the upper surface of the WNx film; patterning the first insulation film, the WNx film and the polysilicon layer, to form a conductive line pattern; and selectively oxidizing the polysilicon layer. With the method, in view of forming the conductive line pattern in the WNx/poly-Si structure, the thermal treatment processes are reduced in number, so that the thermal stress applied to the conductive line pattern is diminished, and thus, a reliability of the semiconductor device is improved.

Abstract: A method is disclosed for forming fine photoresist patterns on semiconductor devices using a modified, two-step dry develop process using a fluorine-containing gas to produce hydrophobic SiOx passivation layers on the sidewalls of the photoresist patterns. These passivation layers increase the structural stability of the fine photoresist patterns and prevent moisture within an air from cohering on the photoresist patterns when the semiconductor substrate is subsequently exposed to the air. Accordingly, the present invention improves the processing margins for very high aspect ratio photoresist patterns resulting in reduced rework and increased yield on very highly integrated semiconductor devices.

Abstract: In a mobile communication system of multi-cell environment, a pico-cell indicator is installed at predetermined positions for easy cell-registration change of a mobile station from a micro-cell service area to a pico-cell service area.

Abstract: A device isolation structure and method for a semiconductor device according to the present invention includes forming first and second trenches by etching predetermined regions of a semiconductor substrate, forming a buried insulating film in the trenches, filling in the trenches by depositing single crystal silicon film on the buried insulating film by a silicon epitaxy method, and forming a field insulating film on portions of the semiconductor substrate between the first and second trenches. The field oxide film isolating the single crystal silicon layers fills the adjacent trenches, thus isolating semiconductor devices, such as a high voltage device and a low voltage device, to be fabricated in the single crystal silicon layers.

Abstract: A method is provided for manufacturing a semiconductor memory device, particularly ferroelectric devices, in which an interlayer dielectric (ILD) layer formed on an upper part of a semiconductor substrate containing a capacitor structure is etched under conditions in which the plasma electron temperature is maintained in a range between 2.0 eV and 4.0 eV to open contact holes to expose the capacitor structure and thereby avoid degradation of the device characteristics.

Abstract: The black level calibration apparatus includes a black level clamp circuit which generates a black level clamp signal based on a calibrated reference voltage. A correlated double sampling/automatic gain control (CDS/AGS) circuit performs sample/hold and automatic gain control operations on an analog image signal based on the black level clamping signals. An analog-to-digital converter converts the analog image output from the CDS/AGS circuit into a digital image signal. A control signal setting circuit compares the black level value of the digital image signal with a black level calibration value, and sets a digital control signal based on the comparison. A reference voltage calibration circuit generates the calibrated reference voltage in accordance with the digital control signal.

Abstract: Disclosed are a semiconductor device and a method for fabricating the same and, more particularly, a method for decreasing the size of semiconductor devices by stacking two substrates, one of which has only memory cells and the other of which has only logic circuits is disclosed. The disclosed method includes forming memory cells on a first semiconductor substrate; forming logic circuits on a second semiconductor substrate; and stacking the second semiconductor substrate on the first semiconductor substrate in order that the memory cells are electrically operable to the logic circuits on the second semiconductor substrate. In the disclosed stacked semiconductor substrate, the logic circuit area is placed on the memory cell area and these two areas are electrically connected by a metal interconnection, thereby decreasing the size of the semiconductor devices.

Abstract: The present invention provides an organic anti-reflective film composition suitable for use in submicrolithography. The composition comprises a compound of chemical formula 11 and a compound of chemical formula 12. The organic anti-reflective film effectively absorbs the light penetrating through the photoresist film coated on top of the anti-reflective film, thereby greatly reducing the standing wave effect. Use of organic anti-reflective films of the present invention allows patterns to be formed in a well-defined, ultrafine configuration, providing a great contribution to the high integration of semiconductor devices. wherein a, b, c, R′, R″, R1, R2, R3, and R4 are those defined herein.