Patents Assigned to IBM Corporation
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Patent number: 7490141Abstract: An Ajax proxy indirection technique enables a local, front-end proxy server to handle Ajax requests from an Ajax client that must be serviced by an external Ajax server in an external domain, instead of a local Ajax back-end server exposing itself to the external domain. The front-end proxy server accepts the Ajax client's request and forwards it to the local Ajax back-end server. The proxy server asks the local AJAX server for the credentials to be used in the “external” AJAX request. The local Ajax back-end server then responds to the proxy server with meta-data for the external domain request that the proxy will make to the external domain. The proxy server uses the credentials of the “external” AJAX request to make the external request to the external Ajax server in the external domain. The proxy server performs any authentication and necessary domain mapping with the external Ajax server before sending a response from the external Ajax server back to the client.Type: GrantFiled: May 15, 2008Date of Patent: February 10, 2009Assignee: IBM CorporationInventors: John Paul Cammarata, Erik John Burckart, Andrew Ivory, Aaron Kyle Shook
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Publication number: 20090031120Abstract: One embodiment of a processor includes a fetch stage, decoder stage, execution stage and completion stage. The execution stage includes a primary execution stage for handling low latency instructions and a secondary execution stage for handling higher latency instructions. A detector determines if an instruction is a high latency instruction or a low latency instruction. If the detector also finds that a particular low latency instruction is dependent on, and destructive of, a corresponding high latency instruction, then the secondary execution stage dynamically fuses the execution of the low latency instruction together with the execution of the high latency instruction. Otherwise, the primary execution stage handles the execution of the low latency instruction.Type: ApplicationFiled: July 23, 2007Publication date: January 29, 2009Applicant: IBM CorporationInventor: Michael Thomas Vaden
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Publication number: 20090023284Abstract: The present disclosure relates to an integrated wafer processing apparatus for fabricating semiconductor chips. This integrated wafer processing system combines the lithography patterning steps and irradiation curing steps of the patternable dielectric into one system. The patternable low-k material of the present disclosure also functions as a photoresist, i.e. is a photo-patternable low-k dielectric material.Type: ApplicationFiled: July 17, 2007Publication date: January 22, 2009Applicant: IBM Corporation (Yorktown)Inventors: Qinghuang Lin, Sampath Purushothaman, Robert Wisnieff
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Publication number: 20090019050Abstract: A calendar system includes a calendar requester client and a calendar owner client that couple to a calendar server via one or more networks therebetween. In one embodiment, when the calendar server denies a particular calendar requester access to the calendar owner's calendar, the calendar server transmits a denial notice to the calendar owner and allows the calendar owner to dynamically add the particular calendar requester to a list of approved requesters on the calendar server.Type: ApplicationFiled: July 12, 2007Publication date: January 15, 2009Applicant: IBM CorporationInventors: Joseph G. Baron, Frank Battaglia, Jerrold Martin Heyman, Michael Leonard Nelson, Andrew Geoffrey Tonkin
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Publication number: 20090018878Abstract: A scheduling system includes a client calendar application that a meeting organizer employs to send a request for free time form to prospective participants of a future meeting via email. The client calendar application receives completed request for participant free time forms back from the prospective participants via email. The client calendar application parses the completed free time forms and determines a consensus free time when all prospective participants are free for the meeting.Type: ApplicationFiled: July 12, 2007Publication date: January 15, 2009Applicant: IBM CorporationInventors: Joseph G. Baron, Frank Battaglia, Jerrold Martin Heyman, Michael Leonard Nelson, Andrew Geoffrey Tonkin
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Patent number: 7472558Abstract: A method of determining optimal air conditioner control is provided that includes determining power consumptions of servers and computer room air conditioners, calculating a number of calories processed by each air conditioner and determining a total number of calories processed as a total heat processed load. Moreover, the method includes determining relevant factors between each of the servers and each of the air conditioners, calculating a percentage of the total heat processed load for each air conditioner, adjusting the corresponding percentage of the total heat processed load for each air conditioner using an operating efficiency curve, calculating a respective power to be consumed by each air conditioner, calculating an efficiency value, determining whether the efficiency value is a maximum efficiency value, and setting each air conditioner at the respective power to be consumed when the efficiency value is the maximum efficiency value.Type: GrantFiled: April 15, 2008Date of Patent: January 6, 2009Assignee: International Business Machines (IBM) CorporationInventor: Izuru Narita
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Publication number: 20080307201Abstract: A processor system executes multiple applet programs within a software application program in an information handling system. The information handling system includes operating system software that manages processor system hardware and software in a multi-tasking environment. In particular, the operating system software manages partitioning of a register file in the processor system to achieve a cooperative relationship among multiple applet programs within respective partitions of the register file. In one embodiment, the operating system software manages unique applet ID's to modify register file partition sizes and locations during applet program instruction text execution. In one embodiment, applet ID masking hardware provides sharing of register file space among multiple copies of applet program code.Type: ApplicationFiled: June 7, 2007Publication date: December 11, 2008Applicant: IBM CorporationInventors: Brian Flachs, Harm Peter Hofstee, Brad William Michael
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Publication number: 20080294881Abstract: An information handling system includes a processor that executes multiple instructions or instruction threads within a software application program. The information handling system includes operating system software that manages processor system hardware and software in a multi-tasking environment. In one embodiment, the operating system manages instruction completion stall analysis software to determine the cause or causes of instruction stalls. In another embodiment, the stall analysis software cooperates with the operating system software to store instruction completion stall event data on a per instruction basis while the application program executes. The operating system software may cooperate with the stall analysis software to store instruction completion stall data in memory for later manipulation by system users or other software.Type: ApplicationFiled: May 24, 2007Publication date: November 27, 2008Applicant: IBM CorporationInventors: Wen-Tzer Thomas Chen, Venkat Rajeev Indukuru, Alexander Erik Mericas, Mysore Sathyanarayana Srinivas
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Publication number: 20080251888Abstract: An integrated circuit (IC) includes power supply interconnects that couple to a power source. The integrated circuit includes electronic devices that perform desired functions and further includes decoupling capacitor circuits that provide noise reduction throughout the integrated circuit. In one embodiment, each decoupling capacitor circuit includes a decoupling capacitor and a switching circuit. The switching circuit connects the decoupling capacitor to the power supply interconnects during a connect mode when the switching circuit detects no substantial decoupling capacitor leakage. However, the switching circuit effectively disconnects the decoupling capacitor from the power supply interconnects during a disconnect mode when the switching circuit detects substantial decoupling capacitor leakage. The decoupling capacitor circuit self-initializes in the connect mode without external control signals and is thus self-contained.Type: ApplicationFiled: April 10, 2007Publication date: October 16, 2008Applicant: IBM CorporationInventors: Vikas Agarwal, Asit S. Ambekar, Sanjay Dubey, Saiful Islam
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Publication number: 20080256345Abstract: An information handling system includes a processor that throttles the instruction fetcher whenever the inaccuracy, or lack of confidence, in branch predictions for branch instructions stored in a branch instruction queue exceeds a predetermined threshold confidence level of inaccuracy or error. In this manner, fetch operations slow down to conserve processor power when it is likely that the processor will mispredict the outcome of branch instructions. Fetch operations return to full speed when it is likely that the processor will correctly predict the outcome of branch instructions.Type: ApplicationFiled: April 10, 2007Publication date: October 16, 2008Applicant: IBM CorporationInventors: Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, Michael Karl Gschwind, Ravi Nair, Robert Alan Philhower, Wolfram Sauer, Raymond Cheung Yeung
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Publication number: 20080243811Abstract: Arrangements and methods for providing for the efficient implementation of ranked keyword searches on graph-structured data. Since it is difficult to directly build indexes for general schemaless graphs, conventional techniques highly rely on graph traversal in running time. The previous lack of more knowledge about graphs also resulted in great difficulties in applying pruning techniques. To address these problems, there is introduced herein a new scoring function while the block is used as an intermediate access level; the result is an opportunity to create sophisticated indexes for keyword search. Also proposed herein is a cost-balanced expansion algorithm to conduct a backward search, which provides a good theoretical guarantee in terms of the search cost.Type: ApplicationFiled: March 29, 2007Publication date: October 2, 2008Applicant: IBM CorporationInventors: Hao He, Philip S. Yu, Haixun Wang
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Publication number: 20080234870Abstract: An irrigation system includes a radio transmitter station that transmits weather prediction information to a geographic region that includes multiple geographic sub-regions. The weather prediction information includes a respective geographic sub-region code for each of the geographic sub-regions for which a weather forecast predicts rain within a predetermined time period. An irrigation apparatus in a particular sub-region activates to water a watering zone at a schedule time. However, if the irrigation apparatus receives the sub-region code for the particular sub-region where the irrigation apparatus is located, the irrigation apparatus does not immediately activate to water the watering zone in one embodiment. The transmitter station may transmit both program content and data content on a common radio frequency signal wherein the data content includes the weather prediction information.Type: ApplicationFiled: March 23, 2007Publication date: September 25, 2008Applicant: IBM CorporationInventors: Glen Edmond Chalemin, Indran Naick, Clifford Jay Spinac, Calvin Lui Sze
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Publication number: 20080235454Abstract: A data processing system includes multiple processors each having multiple processor cores. A core checkstop from a particular processor core indicates that a memory array associated with the particular core exhibits an error. In response to the core checkstop, the system migrates the workload of the particular processor core to another processor core. The system also removes the particular processor core from the current configuration of the system. In response to the core checkstop and error, the system initializes the particular processor core if the error is in a processor memory array associated with the particular core. The system then attempts correction of the error with array built-in self test (ABIST) circuitry. If the ABIST succeeds in correcting the error, the initialization of the particular processor core completes and the system returns the particular processor core to the current processor configuration.Type: ApplicationFiled: March 22, 2007Publication date: September 25, 2008Applicant: IBM CorporationInventors: Michael Conrad Duron, Mark David McLaughlin
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Publication number: 20080235562Abstract: Method and computer program product are provided to encode data for recording onto media whereby modulation and linear constraints from a concatenated code or product code are imposed. A first array of unencoded user data is generated. Each row is modulation encoded to enforce a first modulation constraint; the array is transformed into a second array which is transformed into a third array having predetermined empty locations in each column interleaved with the modulated data. A C2-parity byte is computed for at least some of the empty locations of the third array and a fourth array is generated. C1-parity symbols in each row are computed, generating a fifth array. A second modulation constraint is enforced on each C1-parity symbol in each row of the fifth array, generating a sixth array. The rows of the sixth array are assembled with header and sync fields for recording onto a recording media.Type: ApplicationFiled: March 23, 2007Publication date: September 25, 2008Applicant: IBM CorporationInventors: Evangelos S. Eleftheriou, Robert A. Hutchins, Thomas Mittelholzer, Paul J. Seger
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Publication number: 20080191780Abstract: A virtual electronic fuse (VEF) apparatus and methodology are disclosed that permit the state of an electronic fuse to change from an un-blown state to a blown state and then back to a virtual un-blown state. In one embodiment, the electronic fuse may change from the virtual un-blown state back again to a virtual blown state. The fuse apparatus includes multiple VEFs, each VEF exhibiting a respective address. The fuse apparatus also includes an address pool including multiple address pool locations. A fuse programmer stores an address of one of the VEFs in one or more address pool locations to indicate one or more state changes for a particular VEF. The fuse programmer may also store different VEF addresses in different address pool locations to indicate state changes for different VEFs.Type: ApplicationFiled: February 13, 2007Publication date: August 14, 2008Applicant: IBM CorporationInventors: Robert Christopher Dixon, Michael Wayne Harper
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Publication number: 20080196024Abstract: A client information handling system (IHS) includes a dependency database that stores both installation dependency information and operational dependency information for installed software components and candidate software components. The client IHS also includes a request handler that, in response to a request to change the software configuration of the IHS, checks the dependency database for conflicts between a candidate software component and both installation and operational dependencies that the dependency database stores.Type: ApplicationFiled: February 8, 2007Publication date: August 14, 2008Applicant: IBM CorporationInventors: Janel Guillory Barfield, Eric Philip Fried, Joseph Vernon Lampitt, Kevin William Monroe
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Publication number: 20080191781Abstract: A virtual electronic fuse apparatus and methodology are disclosed that permit the state of an electronic fuse to change from an un-blown state to a blown state and then back to a virtual un-blown state. In one embodiment, the electronic fuse may change from the virtual un-blown state back to a virtual blown state.Type: ApplicationFiled: February 13, 2007Publication date: August 14, 2008Applicant: IBM CorporationInventors: Robert Christopher Dixon, Michael Wayne Harper
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Publication number: 20080189522Abstract: An information handling system includes a processor with multiple hardware units that generate program application load, store, and I/O interface requests to system busses within the information handling system. The processor includes a resource allocation identifier (RAID) that links the processor hardware unit initiating a system bus request with a specific resource allocation group. The resource allocation group assigns a specific bandwidth allocation rate to the initiating processor. When a load, store, or I/O interface bus request reaches the I/O bus for execution, the resource allocation manager restricts the amount of bandwidth associated with each I/O request by assigning discrete amounts of bandwidth to each successive I/O requester. Successive stages of the instruction pipeline in the hardware unit contain the resource allocation identifiers (RAID) linked to the specific load, store, or I/O instruction.Type: ApplicationFiled: February 6, 2007Publication date: August 7, 2008Applicant: IBM CorporationInventors: Gavin Balfour Meil, Leonard Robert, Christopher John Spandikow
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Publication number: 20080189708Abstract: An information handling system (IHS) employs operating system software to manage IHS resources. The operating system software manages software application programs as processes executing within the IHS. The processes run in foreground and background mode within the IHS. Processes running in foreground mode are subject to hang-up events with negative process output results, such as output data loss. In one embodiment, the operating system software supports a “no hang-up now” command for use with processes running in foreground mode. The “no hang-up now” command provides system users the ability to hang-up or log-out of an IHS terminal without negative effects on the current foreground process. A user may invoke the “no hang-up now” command after execution of the foreground process is already underway. The no hang-up command moves the foreground application to the background for continued execution. A signal handler program prevents termination of the background process until the process completes.Type: ApplicationFiled: February 2, 2007Publication date: August 7, 2008Applicant: IBM CorporationInventors: Yinhe Cheng, Hsian-Fen Tsao
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Publication number: 20080183857Abstract: A client information handling system (IHS) connects to a network in a manner that provides transparent network connectivity. In one embodiment, the client IHS includes a polling application that monitors the network connection to determine if the client IHS exhibits a connected status or a disconnected status. An interceptor application in the client IHS permits transmission of a request for a network task from the client IHS if the client IHS currently exhibits a connected status. However, the interceptor application intercepts and stores a request for a network task if the client IHS currently exhibits a disconnected status. At a later time when the client IHS again exhibits a connected status, the interceptor application transmits the stored request over the network. In this manner, the user of the client IHS experiences transparent network connectivity and need not worry with respect to the network connection status of the client IHS at any particular point in time.Type: ApplicationFiled: January 31, 2007Publication date: July 31, 2008Applicant: IBM CorporationInventors: Janel Guillory Barfield, Nancy N. Li