Abstract: An information handling system includes a processor that may perform general purpose register recovery operations after an instruction flush operation that an exception, such as a branch misprediction causes. The processor receives an instruction stream that may include multiple instructions that operate on a particular target register that stores instruction result information. The general purpose register may temporarily store instruction opcode and register bits information for use during dispatch, execution and other operations. The processor includes a recovery buffer unit for use during flush recovery operations. The processor may use recovery valid and recovery pending bits that correspond with each instruction during the register recovery from flush operation.

Abstract: A clock signal duty cycle adjustment circuit includes a duty cycle correction circuit that receives a clock input signal that may need duty cycle correction. The duty cycle correction circuit may derive first and second differential clock signals from the clock input signal. The first and second differential clock signals may exhibit respective voltage offsets. The duty cycle correction circuit includes a voltage offset shift circuit that may shift the voltage offset that one of the first and second differential clock signals exhibits to adjust the effective duty cycle of a clock output signal. The duty cycle adjustment circuit derives the clock output signal from the voltage offset adjusted first and second differential clock signals in response to a duty cycle error signal.

Abstract: An information handling system includes a processor that may perform issue queue virtual load/store instruction operations. The issue queue maintains load and store instructions with a real/virtual dependency flag. The issue queue provides storage resources for real and virtual load/store instructions. Real load/store instructions execute in a load store unit LSU. Virtual load/store instructions are pending execution in the LSU. The LSU may keep track of each virtual load/store instruction within the issue queue by thread, type, and pointer data. Provided that all dependencies are clear for a pending virtual load/store instruction, the LSU marks the pending virtual load/store instruction as real. The pending virtual load/store instruction may then issue to the LSU as a real load/store instruction.

Abstract: An information handling system includes a processor with a bifurcated unified issue queue that may perform unified issue queue VSU store instruction dependency operations. The bifurcated unified issue queue BUIQ maintains VSU store instructions in the form of internal operations data. The BUIQ includes a unified issue queue UIQ 0 and a unified issue queue UIQ 1. The BUIQ may manage a particular VSU store instruction from one UIQ to determine data dependencies and employ the other UIQ to determine address dependencies of that particular VSU store instruction. The UIQs employ a dependency matrix including a dependency array. The dependency array data maintains both data and address dependency information. The particular VSU store instruction issues to execution units such as VSUs for data dependency information and load store units (LSUs) for address dependency information. A particular VSU store instruction may execute to provide data dependency information independent of address dependency information.

Abstract: In the context of middleware products, an arrangement wherein a sender tags messages with authorization information identifying those users or groups who are authorized to view or receive the messages. Thus, even if multiple users will be connected to the same queue for reading messages, only specific receivers/consumers will be able to get the messages. Not only is a comfortable degree of security ensured, but the need to waste system resources, e.g., by using multiple queues for different kinds of messages, is summarily avoided.

Abstract: Graphical User Interface (GUI) automation tools continue to evolve in their sophistication and complexity. However, it is still necessary to tailor such automation to the machine configuration that the test is being run on. This can be a costly and time consuming exercise when developing software for a myriad of different platforms. Broadly contemplated herein, in accordance with at least one embodiment of the invention, are arrangements and processes for recording a test solely on one machine while generating images on all the other available environments.

Abstract: A system and method are provided for enabling a user to search for documents that the user has previously viewed on its local machine. The system includes three main components: the desktop integration module, the index module, and the graphical user interface module. The desktop integration module is an application which monitors documents with which the user interacts for predetermined events, and obtains content data and metadata from the monitored documents. The index module indexes the content data and metadata received from the desktop integration module. The graphical user interface module then permits a user to utilize the desktop integration module and index module by allowing a user to search for a document.

Abstract: A knowledge model of CAD knowledge may be created using a modeling language such as SysML to improve maintainability and re-usability of knowledge, thereby reducing workload. The SysML knowledge model may be stored in a knowledge repository coupled to a knowledge server. The SysML knowledge model may be accessed through the knowledge server. The SysML knowledge model may be associated with elements of a CAD model, and one or more elements of the CAD model may be linked to one or more corresponding elements in the knowledge model. Thus, when a value of one or more elements is changed in the knowledge model, the results of the change are updated substantially immediately in both the CAD model and the knowledge model and other applications using the knowledge model.

Abstract: A method for secure printing comprising receiving a user print request to print information from a computer terminal, wherein the computer terminal is located in a network and is assigned an internet protocol address, prompting the user for approval to instruct a designated printer to commence printing the print request, wherein the designated printer is connected to a network and is assigned an internet protocol address, determining whether the computer terminal and the designated printer are in the same network by comparing the first portion of the computer terminal's internet protocol address with the first portion of the designated printer's internet protocol address, and instructing the designated printer to commence printing if the computer terminal and the designated printer are determined to be in the same network.

Abstract: A symmetric multi-processing (SMP) processor includes a primary interconnect trunk for communication of information between multiple compute elements situated along the primary interconnect trunk. The processor also includes a secondary interconnected trunk that may be oriented perpendicular with respect to the primary interconnect trunk. The processor distributes data on-ramps and data off-ramps across the data lanes of a data trunk of the primary interconnect trunk to enable communication with compute elements and other structures both on-chip and off-chip.

Abstract: A method for managing package delivery may include receiving a plurality of packages. Each package may include a bar code or RFID tag associating the package with personal profile information. A delivery route plan may be generated based on the personal profile information. The estimated delivery time may be transmitted to the recipient in advance of the delivery. An electronic reply communication including a location of the recipient may be received from a notified recipient either confirming the delivery or proposing an alternate delivery time or location. The delivery route plan may be recalculated based on the retrieved personal profile information, the alternate delivery time or location if proposed by the recipient, and/or the current location of the recipient to identify alternate delivery time and location options. A confirmation selecting one of the alternate delivery time and location options or reconfirming the delivery may be received from the recipient.

Abstract: A code coverage tool tests a program under test that executes on a processor of an information handling system (IHS). The code coverage tool may apportion the program under test into code portions of interest that exhibit a user-specified granularity level. A user may request that the code coverage tool change the granularity level of the code portions of interest in real time. The code coverage tool conducts testing of the code portions of interest according to test criteria that the user may specify in real time. The code coverage tool may provide test results for each of the code portions of interest in real time. The code coverage tool may also provide a summary report after providing real time test results for the code portions of interest. The user may specify that the code coverage tool generate real time test results in the form of sensory output, for example auditory output or visual output, for each of the code portions of interest.

Abstract: Methods for making solder balls, which can be used to bump semiconductor wafers are disclosed. Methods for bumping semiconductor wafers with the solder balls are also disclosed. The solder balls can be made using an injection molded soldering (IMS) process.

Abstract: A system for preventing unauthorized viewing of content displayed on a computer display is presented. Once the system is activated, a computer user's eyes are tracked. If some source of interruption enters the vicinity of the user, the computer user will reflexively glance or look at the distraction, which accordingly results in the user removing his focus from the content on the computer display. As the user's focus is diverted from the display due to the interruption, the eye tracking detects this. In response to the detected removal of focus, the computer display is locked out extremely rapidly such that the content is no longer displayed.

Abstract: A method of a method of replacing bad sectors in a Hard Disk Drive comprises detecting bad sectors on the Hard Disk Drive; remapping the bad sectors to an auxiliary data storage device comprising an Magnetoresistive Random Access Memory connected to the Hard Disk Drive; and storing data on the auxiliary storage device.

Abstract: A release film for soft composite materials is provided. The release film contains a film with a closely packed self-assembled monolayer. A method of applying soft composite materials to a substrate without loss of the soft composite material to the release film is also provided. The method is useful in applications such as applying thermal pastes to semiconductor packaging.

Abstract: A system, method and program product for processing a multiplicity of data update requests made by a customer. All of the data update requests are grouped into a plurality of blocks for execution by a data processor. The data update requests within each of the blocks and from one of the blocks to a next one of the blocks are arranged in an order that the data update requests need to be executed to yield a proper data result. Each of the blocks have approximately a same capacity for the data update requests. The capacity corresponds to a number of the data update requests which the data processor can efficiently process in order before processing the data update requests in the next one of the blocks. Then, the data processor processes the data update requests within the one block in the order. Then, the data processor processes the data update requests within the next block in the order. The order is an order in which the data update requests were made.

Abstract: A test system or simulator includes an IC test application sampling software program that executes test application software on a semiconductor die IC design model. The test application sampling software includes trace, simulation point, CPI error, clustering and other programs. IC designers utilize the test application sampling software to evaluate the performance characteristics of IC designs with test software applications. The test application sampling software generates basic block vectors (BBVs) and fly-by vectors (FBVs) from instruction trace analysis of test application software. The test application sampling software analyzes microarchitecture dependent information that it uses to generate the FBVs. Test application sampling software generates a reduced representative test application software program from the BBV and FBV data utilizing an instruction budgeting method.

Abstract: An information handling system employs a processor that includes a thread priority controller. An issue unit in the processor sends branch issue information to the thread priority controller when a branch instruction of an instruction thread issues. In one embodiment, if the branch issue information indicates low confidence in a branch prediction for the branch instruction, the thread priority controller speculatively increases or boosts the priority of the instruction thread containing this low confidence branch instruction. In the manner, should a branch redirect actually occur due to a mispredict, a fetcher is ready to access a redirect address in a memory array sooner than would otherwise be possible.

Abstract: An information handling system employs a processor that includes a thread priority controller. The processor includes a memory array that stores instruction threads including branch instructions. A branch unit in the processor sends flush information to the thread priority controller when a particular branch instruction in a particular instruction thread requires a flush operation. The flush information may indicate the correctness of incorrectness of a branch prediction for the particular branch instruction and thus the necessity of a flush operation. The flush information may also include a thread ID of the particular thread. If the flush information for the particular branch instruction of the particular thread indicates that a flush operation is necessary, the thread priority controller in response speculatively increases or boosts the priority of the particular instruction thread including the particular branch instruction.