Abstract: A method of holding information for identifying a cause for an object becoming problematic and presenting the information to a user. The method ascertains the cause of memory consumption by a program in a computer system. This method includes: acquiring a first call path related to the creation of an object from a memory; acquiring a second call path related to the connection to the object from the memory; and determining a common part of the acquired first and second call paths, wherein the common part indicates the cause in the program.

Abstract: A virtual tape server (VTS) and a method for managing shared first level storage, such as a disk cache, among multiple virtual tape servers are provided. Such a system and method manage first level storage to accommodate two or more host processing systems by maintaining adequate free space in the cache for each host and by preventing one host, such as a mainframe, from taking over free space from another host, such as a Linux system.

Abstract: An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. When the L2 cache memory finishes servicing the interrupting load request, the L2 cache memory may return to servicing the interrupted store request at the point of interruption.

Abstract: An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. When the L2 cache memory finishes servicing the interrupting load request, the L2 cache memory may return to servicing the interrupted store request at the point of interruption. The control logic determines the size requirement of each load operation or store operation. When the cache memory system performs a store operation or load operation, the memory system accesses the portion of a cache line it needs to perform the operation instead of accessing an entire cache line.

Abstract: A method, system, and computer program product are provided for controlling liquid-cooled electronics, which includes measuring a first set point temperature, Ta, wherein the Ta is based on a dew point temperature, Tdp of a computer room. A second set point temperature, Tb, is measured, wherein the Tb is based on a facility chilled liquid inlet temperature, Tci, and a rack power, Prack, of an electronics rack. A Modular Cooling Unit (MCU) set point temperature, Tsp, is selected. The Tsp is the higher value of said Ta and said Tb. Responsive to the selected Tsp, a control valve is regulated. The control valve controls a flow of liquid that passes through a heat exchanger.

Abstract: An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. The L2 cache memory includes dual data banks so that one bank may perform a load operation while the other bank performs a store operation. The cache system provides a single dispatch point into the data flow to the dual cache banks of the L2 cache memory.

Abstract: An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. The L2 cache memory includes dual data banks so that one bank may perform a load operation while the other bank performs a store operation. The cache system provides dual dispatch points into the data flow to the dual cache banks of the L2 cache memory.

Abstract: A modeling system includes a processor with software that performs static timing analysis (STA) on a design model. STA software executes a static timing analysis (STA) run with shortened clock cycles to model full cycle clock variability. Designers or other entities interpret the results of the shortened STA run data by performing modeling on the output data to generate slack data for design model data paths. STA software executes an STA run with an extended clock cycle to automatically separate half cycle data path (HCDP) slack data from full cycle data path (FCDP) slack data. The full and half cycle clock variability method may automatically adjust slack data for all half cycle data paths (HCDP)s to account for the additional half cycle variation (AHCV) and half cycle clock edge variability that may penalize the design model results in a real hardware implementation.

Abstract: A RAID system is provided for detecting and correcting dropped writes in a storage system. Data and a checksum are written to a storage device, such as a RAID array. The state of the data is classified as being in a “new data, unconfirmed” state. The state of written data is periodically checked, such as with a timer. If the data is in the “new data, unconfirmed” state, it is checked for a dropped write. If a dropped write has occurred, the state of the data is changed to a “single dropped write confirmed” state and the dropped write error is preferably corrected. If no dropped write is detected, the state is changed to a “confirmed good” state. If the data was updated through a read-modified-write prior to being checked for a dropped write event, its state is changed to an “unquantifiable” state.

Abstract: A system that automatically prompts a computer user about a known limitation of a product component, such as a software component. Generally, there is contemplated herein a method including providing a physical computing device, running software in the physical computing device, detecting whether the software has a known limitation, and automatically providing an advisory responsive to detecting a known software limitation.

Abstract: In software development, the provision of a testing tool which includes a method for defining a data source dynamically during an execution run, instead of programming such a definition within test script.

Abstract: A weighted combining scheme exploits information from two servo channels operating in parallel. A timing-based servo module comprises two synchronous servo channels coupled respectively to receive two digital servo signals read from a data tape. Both channels have outputs for an unweighted parameter estimate and for a measure of the channel reliability. A weight computation module provides first and second weight signals using the measures of channel reliability from the servo channels. An offset computation module provides first and second offset terms which are summed with the unweighted parameter estimates. Multiplying nodes receive the unweighted parameter estimates and the weight signals and outputs offset weighted parameter estimates. A summing node receives the offset weighted parameter estimates and outputs a combined offset weighted parameter estimate to a servomechanism.

Abstract: A weighted combining scheme exploits information from two servo channels operating in parallel. A timing-based servo module servo module comprises two servo channels coupled respectively to receive two digital servo signals read from a data tape. Both channels have outputs for an unweighted metric and for a measure of the channel reliability. A weight computation module provides first and second weight signals using the measures of channel reliability from the servo channels. A first multiplying node receives a first unweighted metric and a first weight signal and is operable to output a first weighted metric. A second multiplying node receives a second unweighted metric and a second weight signal and outputs a second weighted metric. A summing node receives the first and second weighted metrics and outputs a combined weighted metric to an LPOS word decoder.

Abstract: A 16-State adaptive NPML detector is provided for a tape drive which addresses weaknesses of a conventional fixed, 8-state EPR4 detector. Rather than having a fixed target channel, the detector is programmable to allow a range of target channels and can support “classical” partial response channels such as PR4 or EPR4 by programming predictor or whitening filter coefficients. In one embodiment, two filter coefficients may be set via XREG inputs or dynamically determined through the use of an LMS algorithm allowing the detector to adapt the predictor coefficients as data is being read. Another embodiment provides a detector for an EPR4 target in which the whitening filter has one coefficient. Components of the detection system include the detector itself, an LMS engine, a coefficient engine and a noise predictive or whitening filter. Coefficients from the LMS engine may be loaded or stored dynamically based upon conditions in the tape drive.

Abstract: Writing data to magnetic tape is performed by receiving data from a host, establishing sub data sets, computing C1 and C2 ECC, forming Codeword Quad sets, writing a beginning Data Set Separator to a magnetic tape, writing a plurality of contiguous instances of the CQ Set to the magnetic tape and writing a closing DSS. The number of instances of each Codeword Pair is increased, thereby allowing the benefits of writing short tape records and improving reading reliability while reducing susceptibility to mis-tracking errors and large defects, and while reducing the negative impact on data reliability. Otherwise unused latency times are utilizing and therefore no performance penalty is incurred.

Abstract: For writing data to multi-track tape, a received data set is received and segmented into unencoded subdata sets, each comprising an array having K2 rows and K1 columns. For each unencoded subdata set, N1?K1 C1-parity bytes are generated for each row and N2?K2 C2-parity bytes are generated for each column. The C1 and C2 parity bytes are appended to the ends of the row and column, respectively, to form encoded C1 and C2 codewords, respectively. All of the C1 codewords per data set are endowed with a specific codeword header to form a plurality of partial codeword objects (PCOs). Each PCO is mapped onto a logical data track according to information within the header. On each logical data track, adjacent PCOs are merged to form COs which are modulation encoded and mapped into synchronized COs. Then T synchronized COs are written simultaneously to the data tape where T is the number of concurrent active tracks on the data tape.

Abstract: Methods, logic, apparatus and computer program product write data, comprising less than a full Data Set, to magnetic tape. Data is received from a host, a do-not-interleave command is issued and C1 and C2 ECC are computed. Codeword Quad (CQ) sets are then formed. At least one CQ set of the Data Set is written to a magnetic tape in a non-interleaved manner and a Data Set Information Table (DSIT) is written to the magnetic tape immediately following the at least one written CQ set. An address transformation may be used to cancel interleaving. Writing a CQ set may include writing a plurality of contiguous instances of the CQ set to the magnetic tape to maintain the effectiveness of ECC capability.

Abstract: Conventional C2 coding and interleaving for multi-track data tape in LTO-¾ do not support recording data onto a number of concurrent tracks which is not a power of two. Higher-rate longer C2 codes, which do not degrade error rate performance, are provided. An adjustable format and interleaving scheme accommodates future tape drives in which the number of concurrent tracks is not necessarily a power of two. A data set is segmented into a plurality of unencoded subdata sets and parity bytes are generated for each row and column. The parameters of the C2 code include N2 as the least common multiple of the number of possible tracks to which codeword objects are to be written. COs are formed from N2 C1 codewords, mapped onto a logical data track according to information within headers of the CO and modulation encoded into synchronized COs which are written to the tape.

Abstract: Methods are provided for managing data encryption for a data storage library. An implementation assessment is performed for a customer and, in response to the implementation assessment, a set of customizations are generated for an encryption command communications appliance to enable the appliance to communicate with an encryption-capable storage device and a data storage library controller within the data storage library and with an encryption key manager (EKM) coupled to the data storage library. The encryption command communications appliance is configured with the set of customizations and the configured encryption command communications appliance is installed in the data storage library coupled to the library controller, the storage device and the EKM.

Abstract: An encryption communications appliance provides data encryption management for a data storage library. The appliance is coupled to an encryption-capable storage device, a data storage library controller within the data storage library and with an encryption key manager (EKM). The encryption command communications appliance intercepts encryption key requests from the data storage device and transparently forwards the requests to the EKM. The appliance also forwards transparently communications between the library controller and the data storage device.