Abstract: Circuit boards or cards containing metallic layers on opposite major surfaces of a dielectric substrate whereby electrical and/or thermal interconnection between the metallic layers is provided in vias that extend through one of the metallic layers, and the dielectric substrate and into the other metallic layer.

Abstract: A structure for guiding millimeter wave radiation employs a resonant coplanar transmission line on a transparent substrate. A very short, picosecond, pulse is generated on the transmission line. By having the upper half plane air, the pulse will radiate into the substrate and be guided as millimeter wave from a distributed source and formed as a point source of radiation.

Abstract: A current limiting clamp circuit for providing a clamped voltage at a node and including a P-type MOS transistor and several N-type MOS transistors which are connected in series between the drain of the P-type MOS transistor and ground, with one of the N-type transistors having its gate and drain connected to the drain of the P-type transistor, and having its source connected to the node. In another embodiment, the current limiting clamp circuit includes a pair of P-type transistors and several N-type transistors, with one of the P-type transistors having its source connected to a power supply, its gate connected to ground and its drain connected to the source of the other P-type transistor which has its gate and drain connected to the node.

Abstract: A multi-dimensional, multi-nodal routing mechanism is described for relaying information from node to node using a header consisting of route descriptor bits. Each node's receiver/transmitter pair changes states as the information is guided to the destination node. The message is propagated over several nodes simultaneously to traverse the nodes and reach the destination node quickly. When the final node is reached, all alternate communication routes are freed.

Abstract: In an 80386/82385 microcomputer system, the timing requirements placed on non-cache memory components by the 82385 are more stringent than the timing requirements placed on the non-cache memory components by the 80386. The present invention operates on the 82385 cache write enable (CWE) signals, and delays those signals in the event of a read miss. Delaying the CWE signals relaxes the timing requirements placed on non-cache memory components and at the same time does not impact wait state parameters for read miss operations.

Abstract: A system for transferring a plurality of data items (bytes) between a source device and a destination device. The system loads data items from the source device into a register so as to align the data items with the storage locations of the destination device, transfers the aligned data items to the destination device, rolls-down, in sequence, any remaining data items in the register to least significant storage locations thereof; loads a full data word, which includes a predetermined number N of data items, from the source device into the register starting with the most significant storage location of the register containing a data item; and transfers N or fewer data items stored in the register, starting from the least significant storage location of the register to the destination device.

Abstract: A method and apparatus are provided for measuring flying height changes of a transducer head relative to a disk surface of a rotating disk in a disk file. A predetermined pattern is written on at least one predetermined region of the disk file. The predetermined region is normally not rewritten during operation of the disk file. At least one readback signal is sensed from at least one predetermined region of the disk surface. A plurality of sample values are identified corresponding to each readback signal. A change in the flying height is calculated utilizing the identified sample values. A frequency equalization number K can be utilized to calculate the magnitude and sign of the flying height change. Alternatively, real-time digital analysis of a predetermined pattern written on at least one predetermined region of the disk surface can be utilized to calculate the magnitude and sign of the flying height change.

Abstract: A nested frame communication protocol for communicating between computers. According to the nested frame communication protocol of the present invention, the computers communicate by transferring frames over communication links. The transmission of low priority frames may be interrupted in order to transmit high priority frames. After the transmission of the high priority frames is complete, the transmission of the low priority frames resumes. Processing states relating to interrupted frame transmissions are saved when the frame transmissions are interrupted. The processing states are restored when the interrupted frame transmissions are resumed.

Abstract: A systematic method for detecting which head in a multiple head storage device contains errors and may be misaligned, and correcting for misalignment so that the data can be recovered. The apparatus includes a data buffer for storing a block of interleaved data read from the multiple head storage device, status bits, error detection circuitry for determining from the interleaved data, which if any of the heads is misaligned and for setting the status bits, data recovery control logic responsive to the status bits for sending control signals to the multiple head storage device for causing the misaligned head to move its position by small increments and to read data until the status bits indicate that the misaligned head has become aligned, and circuitry responsive to the status bits for writing data from the newly realigned head over the data which was read when that head was misaligned.

Abstract: A computer-based system and method for building a Rete based network. The computer-based system comprises a first module for inputting rules into the computer-based system, wherein each of the rules may have arbitrary specified tests therein. The computer-based system further comprises a second module responsive to the first module for generating a data structure indicative of each of the inputted rules. The computer-based system further comprises a third module, responsive to the second module for storing each of the inputted rules and a fourth module responsive to the third module for constructing a Rete network for the rules. Further disclosed is system and method for allowing an expert system developer to enter rules that are formatted in conjunctive, disjunctive and or negated form.

Abstract: A molecular restricter for inhibiting or preventing gas molecules from flowing past a point, such as a piece of optical equipment, substantially without inhibiting particles mixed therewith from passing therethrough is described. The molecular restricter has a plurality of elongated cells with each end open to permit the particles to pass through. However the width of the cell must be less than the mean free path .gamma. of the molecules under the conditions the restricter is to be used with. In one embodiment, the length of the cell is at least ten times longer than its width. The cells are arranged adjacent to each other and in parallel orientation. The walls of each cell must also be parallel to permit free transmission of the particles or light therethrough.

Abstract: A programmable computer user input/output (I/O) system having a multiple degree-of-freedom magnetic levitation (maglev) device with a matched electrodynamically levitated flotor and stator combination and an electrodynamic forcer means for receiving coil currents for applying controlled magnetic forces mutual to the flotor and stator. A sensing means measures the relative position and orientation of the flotor and stator. The I/O system includes a maglev I/O device control software module for measuring the relative movement of the flotor-stator combination of the maglev device and for controlling the coil currents provided to the electrodynamic forcer means. At least one active device model module, comprising a software representation of a mechanical I/O device, controls the maglev I/O device control software module to generate signals which emulate the mechanical I/O device represented by the active device model.

Abstract: A fully redundant safety interlock system is provided comprising, means for detecting the loss of light on a fiber optic link; controller means, coupled to said means for detecting, for determining the safety condition of the link based on the output of said means for detecting, and for controlling the radiant energy output of an optical transmitter, based on the determined safety condition, via redundant output control signals; and means, coupled to said controller means, responsive to said redundant control signals, for interconnecting the output of said controller means to transmitter drive circuitry to thereby adjust the radiant energy output by the transmitter. According to a preferred embodiment of the invention, the controller means includes an electronic implementation of two independent state machines, each of which redundantly determines the connection state of the optical link between two optical link cards.

Abstract: The present invention is a circuit and method for reducing switching losses in a full bridge, resonant transition, switching power converter. The converter circuit includes a bridge switching circuit having an FET switch in each leg of the bridge. Each FET has a parasitic drain-to-source capacitance. The primary of a power transformer is connected across the bridge. Two secondary windings of the transformer are connected in a center-tapped configuration. A saturable reactor and a rectifier is connected in series with each secondary winding. A control means controls the conduction interval of the FET switches to produce a first and a second half-cycle of converter operation, each half-cycle including an on-time and a free-wheeling interval. The saturable reactors force unequal current distribution in the secondary windings during the free-wheeling intervals such that a primary current is caused to flow.

Abstract: A high conduction cooling structure useful for dissipating heat from integrated circuit devices includes a cooling base (10), a bulk heat transfer element (18), adjacent spaced apart cooling fins (14 and 16), and a bimetallic strip (22). The cooling base (10) is positioned in heat transfer relationship with an integrated circuit device and as it increases in temperature, the bimetallic strip (22) flexes outwardly and contacts the cooling fins (14 and 16). The contact created with the cooling fins (14 and 16) allows for more efficient transfer of thermal energy.

Abstract: A method and apparatus to encapsulate a device and joints coupled to conductive leads with an encapsulating material. A fixture has a recess to hold via a vacuum the device in place. Conduits in the fixture supply air around the device to form an air dam that flows outward around the device and the leads. A nozzle supplies a metered amount of material to the surface of the device. By controlling the temperature of the fixture and/or the air forming the air dam, the flow of material can be confined to the surface of the device and the joints as it cures. The method can also provide encapsulant edge capping to reduce device stresses.

Abstract: A multi-bus microcomputer system includes a cache subsystem and an arbitration supervisor. A CPU is provided with a PREEMPT signal source which generates a preempt signal in CPU cycles extending beyond a specified duration. The preempt signal is effective at any device having access to the bus to initiate an orderly termination of the bus usage. When that device signals its termination of bus usage, the arbitration supervisor changes the state of an ARB/GRANT conductor, which had been in the grant phase, to the arbitration phase. During the arbitration phase each of the devices (other than the CPU) cooperates in an arbitration mechanism for bus usage during the next grant phase. On the other hand, the CPU, having asserted preempt, responds to a signal indicating initiation of the arbitration phase by immediately accessing the system bus.

Abstract: Any incompatibility between pipelined operations (such as is available in the 80386) and dynamic bus sizing (allowing the processor to operate with devices of 8-, 16- and 32-bit sizes) is accommodated by use of an address decoder and ensuring that device addresses for cacheable devices are in a first predetermined range and any device addresses for non-cacheable devices are not in that predetermined range. Since by definition cacheable devices are 32-bit devices, pipelined operation is allowed only if the address decoder indicates the access is to a cacheable device. In that event, a next address signal is provided to the 80386. This allows the 80386 to proceed to a following cycle prior to completion of the previous cycle. For accesses which are to devices whose address indicate they are non-cacheable, a next address signal is withheld until the cycle is completed, i.e. without pipelining.

Abstract: A gradiometer utilizes at least three vector magnetometers (preferably SQUIDs) to measure a magnetic field gradient. The gradiometer includes a reference magnetometer and a plurality of sensor magnetometers, wherein the reference magnetometer (SQUID) used to cancel background magnetic fields from outputs of the sensor magnetometers via a feedback loop provided with a signal from the reference magnetometer. Similarly, higher order gradiometers can be built using a reference magnetometer cube and a plurality of sensor magnetometer cubes.

Abstract: A method of forming an LDD field effect transistor with an inverted "T"-gate structure in which consecutive, conformal layers of polysilicon, metal and nitride or oxide are deposited to fill the recess in a composite interconnect layer on top of a trench isolated region of a semiconductor substrate. These conformal layers successively decrease in thickness and are selectively etched in two steps to form a self-aligned inverted T structure. A first reactive ion etch (RIE) step preferentially etches the exposed outer polysilicon to a certain depth. During a second step RIE the polysilicon layer is completely etched down to the a gate oxide surface and the metal layer is preferentially etched so that subtends only the remaining nitride or oxide cap.