Abstract: A technique for performing joins in parallel on a multiple processor database system effectively deals with data skew. The join operation is performed in three stages with an optional fourth stage. The first stage is a preparatory stage, the detail of which depends on the underlying join algorithm used. This preparatory stage provides pre-processing the results of which are used in the following stage as the basis for defining subtasks for the final join operation. The data provided in the first stage is used in the second stage to both define subtasks and to optimally allocate these subtasks to different processors in such a manner that the processors are close to equally loaded in the final join operation, even in the presence of data skew. This second stage is an assignment stage the details of which depend on the underlying join algorithm.

Abstract: Two methods for wet etch removing an etch stop layer without leaving an undesired undercut are disclosed. In the first method, a reactive ion etch is stopped on an etch stop layer. The exposed etch stop is wet etch removed, leaving an undesirable undercut. The undercut is filled by chemical vapor deposition of a fill material. The filler is then etched to leave a smooth aperture without undercuts. This last etch may be a sputter etch followed by a plasma etch. In the second method, a reactive ion etch is stopped on an etch stop layer as in the first method. Sacrificial sidewalls are then formed within the aperture. The exposed etch stop layer is then removed by wet etching, the positioning of the sidewalls serving to prevent undercutting of the etch stop layer. Finally, the sacrificial sidewalls are etched.

Abstract: An inference engine device adapted for use in a computer-controlled expert system, the computer-controlled expert system having a computer and a knowledge base of objects and rules, the objects having known values and unknown values, the rules having at least one test against an object or objects and configured in a Rete based network. The inference engine is comprised of a first module with a function of storing instructions for the computer; a second module, associated with the first module, that is comprised of a function for instructing the computer to perform forward reasoning with the objects having known values and another function for generating a conflict set; a third module, associated with the first module, that has a function of instructing the computer to perform backward reasoning about the objects having unknown values; and a fourth module, associated with the first module, that determines whether the first or second module is being executed by the computer.

Abstract: A system for measuring transient friction of a head-disk interface in a magnetic disk storage device employs a servo system for accurate measurements. A first movable member carries a slider simulating a magnetic head which rests on a disk when said disk is at rest. The movable member is movably mounted to a second fixed member. A frictionless detector detects a displacement of the movable member relative to a position of the fixed member produced by a force due to friction when the disk spins. A servo system maintains a fixed distance between first and second members in response to an output from the detector and moves the movable member in response thereto. The output is taken from the servo system and provides a signal proportional a force due to friction exerted on said movable member.

Abstract: New photosensitive polyimide compositions and processes of using the same in the fabrication of electronic components are provided. These compositions are comprised of ##STR1## containing polyamic acids and/or the corresponding hydroxy-polyamic esters, or hydroxypolyimides and a photoactive component as an additive or as covalently bonded functionality on the polymer chain. These compositions provide positive or negative patterning options and may be used as conventional resist materials, as imageable dielectric or passivating layers, as high Tg ion implant masks or as imageable lift-off layers in the fabrication of multilevel metal structures.

Abstract: Increased etching rates are obtained by plasma etching wherein the power is applied in a cyclical or oscillating mode.

Abstract: A conceptual design tool uses a sketch sheet approach on a computer display to enter the functional design of a product, thereby encouraging the designer to use a top down approach to the design process. The user keys in part descriptions, and the system automatically draws a hierarchical tree structure on the computer display. The user is then prompted to consider, part by part, all of the parts in the product. A series of pop-up menus guide the user through manufacturing and planning for the part. Based on the data input by the user, the system then generates a qualified parts list and computes an estimated cost figure for the product using manufacturing information gathered by the conceptual design tool during product release planning.

Abstract: Photocurable compositions with, as photoinitiator, sulfonium salts of the formula: ##STR1## wherein Ar is a fused aromatic radical; R.sub.1 is a divalent organic bridge; each R.sub.2 and R.sub.3 individually is an alkyl, aryl, alkaryl, aralkyl or substituted aryl, provided that not more than one of R.sub.2 and R.sub.3 is alkyl; and A is a non-nucleophilic anion; use thereof and preparation thereof.

Abstract: A circuit board with insulated wire thereon is encapsulated with a photocurable adhesive composition comprising a phenoxy resin; a reaction product of an unsaturated carboxylic acid and epoxidized non-linear novolak; reaction product of an unsaturated carboxylic acid and a tetrabrominated diglycidyl ether of a phenol; monohydroxy dipentaerythritol acrylate and/or pentaerythritol tetraacrylate; polyethylenically unsaturated compound; and photoinitiator, and optionally, hexamethylol melamine-formaldehyde; and/or a thixotropic agent.

Abstract: An inspection system employing high collection efficiency energy filtered backscatter electrons. At least two detectors are positioned relative to the sample at spaced locations. Each detector has a canister with a fiberoptic bundle mounted therein. A scintillator detector is mounted at the end of the fiberoptic bundle. A ground grid is mounted at an opening of the canister in axial alignment with the scintillator detector. An energy filter is interposed between the scintillator detector and the ground grid. The energy filter is an electrostatic retarding potential grid to permit detection of only high energy backscatter electrons. The geometry of the detectors relative to the specimen together with the conical shape of the detector housing achieves maximum collection efficiency of the targeted electrons.

Abstract: A combined linear-rotary direct drive step motor, having a rotary section and a linear section in a single housing, comprising a cylindrically shaped variable reluctance linear step motor; a modified hybrid permanent-magnet rotary step motor; and a common shaft shared by said linear step motor and said rotary step motor. The teeth of the rotary motor are circumferentially spaced around the stator pole faces and rotor; while in the linear portion of the motor, the teeth are longitudinally spaced along the face of the stator poles and rotor. Except for the teeth, the shape of the stator poles in the rotary and linear sections are identical. The laminated stators and rotors reduce eddy current losses at high stepping speeds. The stator coils of both motor sections are separate and can be energized independently allowing any combination of rotary or linear motion. According to alternate embodiments of the invention, the rotor is fabricated from stacked laminations, in a waffle board like configuration.

Abstract: The base circuit comprises a self-referenced preamplifier (31) of the differential type connected between first and second supply voltages and a push-pull output buffer stage connected between second and third supply voltages. The push-pull output buffer stage comprises a pull-up transistor and a pull-down transistor connected in series with the circuit output node coupled therebetween. These transistors are driven by complementary and substantially simultaneous signals S and S supplied by the preamplifier. Both branches of the preamplifier are tied at a first output node (M). The first branch comprises a logic block performing the desired logic function of the base circuit that is connected through a load rsistor to the second supply voltage. The logic block consists of three parallel-connected input NPN transistors, whose emitters are coupled together at the first output node for NOR operation.

Abstract: A method and apparatus are provided for uniquely identifying integrated circuit chips adapted for use with scan design systems and scan testing techniques. A predetermined identification number corresponding to each LSI chip to be identified is assigned. Each predetermined identification number has a predefined format. The assigned identification number is stored in a plurality of predefined shift register latches (SRLs) in the corresponding LSI chip to be identified. Then the LSI chip is identified by selectively reading out the stored predetermined identification number.

Abstract: The present invention comprises the use of a copper/nickel containing alloy composition or application of a protective nickel alloy coating to copper current-carrying leads to prevent electrolytic migration between tape automated bonding (TAB) package leads.

Abstract: The detection of DTMF tones is improved in a three-step process: first testing even-numbered samples; then testing odd-numbered samples, and finally testing for tone quality (time interval and frequency stability).

Abstract: A method to preserve system resources during the execution of distributed application programs in an SNA type data processing network that supports program to program communication between an Intelligent Work Station (IWS) and a host processor in accordance with SNA Logical Unit 6.2 protocols when a Virtual Machine Pool Manager exists at the host processor and functions to,(1) create a pool of virtual machines at the host processor that are brought to a run ready state prior to any program to program communciation,(2) dynamically assign an idle run ready virtual machine to process each request from the IWS involving one application program so that sequential requests from the one program are assigned to different ones of the idle virtual machines and run concurrently, and3) provide a Pool Manager Data Structure for use by the Pool Manager during the step of dynamically assigning the idle run ready virtual machines in the pool.

Abstract: The latch (100) includes a catch (102) having a beveled edge (102A). An aperture (104) receives a downward force to release the catch from the lip (106A) of a housing (106). A stop (108) limits the downward movement of the latch. A retaining tab (110) traps the latch within the door pocket and limits the upward movement of the latch. The retaining tab includes a beveled surface (110A) to facilitate the insertion of the latch into the pocket. A cantilever spring (112) exerts an upward force on the latch when compressed. The latch, including all of its associated parts, can be plastic injection molded in a single-action mold. The door (200) includes a substantially parallelepiped pocket (202) having an opening at the top to receive the latch. The pocket includes a front aperture (202FA) in the upper, front surface (202F) of the pocket, and a rear aperture (202RA) in the lower, opposing rear surface (202R).

Abstract: A method for processing distributed application programs in SNA type networks including a host system having a virtual machine type Operating System and an Intelligent Work Station (IWS) provided with an Operating System that is capable of running two distributed application programs concurrently, in which two idle virtual machines, from a pool of run ready virtual machines that are created and managed by a Virtual Machine Pool Manager (VMPM), are each assigned to process a different one of the two application programs concurrently to prevent the distributed application programs from being serialized on one virtual machine at the host even though both application programs are being invoked by requests at the IWS terminal involving the same USER ID.

Abstract: A delay circuit for receiving a number of input signals and for providing a delay in accordance with the input signals. The delay circuit includes: an output circuit for producing a first output signal when a node is above a threshold voltage, and for producing a second output signal, which is different from the first output signal, when the node is below the threshold voltage; a device for maintaining the node voltage at a level which is above the threshold voltage so that the output circuit produces the first output signal; and a plurality of switching devices for causing, the node voltage to decrease below the threshold voltage so that the output circuit produces the second output signal. Depending on which one of the switching devices is rendered conductive, the node voltage will decrease at a different rate, thereby causing the output circuit to produce the second output signal at different delay times.