Patents Assigned to IBM
  • Publication number: 20120023280
    Abstract: A method and data processing system enables scheduling of atomic operations within a Peripheral Component Interconnect Express (PCIe) architecture during page migration. In at least one embodiment, firmware detects the activation of a page migration operation. The firmware notifies the I/O host bridge, which responds by setting an atomic operation stall (AOS) bit to a pre-established value that indicates that there is an ongoing migration within the memory subsystem of a memory page that is mapped to that I/O host bridge. When the AOS bit is set to the pre-established value, the I/O host bridge prevents/stalls any received atomic operations from completing. The I/O host bridge responds to receipt of receipt of an atomic operation by preventing the atomic operation from being initiated within the memory subsystem, when the AOS bit is set to the pre-established value. The AOS bit is reset when the migration operation has completed.
    Type: Application
    Filed: July 20, 2010
    Publication date: January 26, 2012
    Applicant: IBM CORPORATION
    Inventors: Eric N. Lais, Steve Thurber
  • Publication number: 20120023302
    Abstract: A method and data processing system enables scheduling of atomic operations within a Peripheral Component Interconnect Express (PCIe) architecture during page migration. In at least one embodiment, firmware detects the activation of a page migration operation and sets a migration bit in the page table. When the PCIe Host Bridge (PHB) receives an atomic operation, the PHB checks the migration bit associated with the memory page targeted by the atomic operation and if the migration bit is set, the PHB buffers the atomic operation and sets an atomic operation stall (AOS) bit associated with the buffer. The atomic operation is stalled until the migration bit is reset, at which time the PHB resets the AOS bit of the buffer. The atomic operations are permitted to continue when the migration bit of the target memory page is not set, and along with DMA operations, may bypass other stalled atomic operations.
    Type: Application
    Filed: July 20, 2010
    Publication date: January 26, 2012
    Applicant: IBM CORPORATION
    Inventors: Richard L. Arndt, Eric N. Lais, Steve Thurber
  • Publication number: 20120016885
    Abstract: Embodiments of the invention relate to techniques for personalized tag recommendation for enterprise social bookmarking systems. According to one embodiment of the invention, a method comprises computing at least one set of candidate tags for a document in accordance with at least one factor, and combining the at least one set of candidate tags from different factors into an overall recommendation list of candidate tags. At least one suggested tag from the overall recommendation list is returned as a result of the combination. At least one applied tag that is applied to the document by a user of a computer system is recorded, and the combination is adjusted based on the at least one applied tag.
    Type: Application
    Filed: July 16, 2010
    Publication date: January 19, 2012
    Applicant: IBM CORPORATION
    Inventors: Hongxia Jin, Qihua Wang
  • Publication number: 20120005142
    Abstract: According to one embodiment of the present invention, a method for online convex optimization is provided. The method includes performing a step that relies on the selection of x at a time t (xt), where x is a variable involved with the step. A resulting cost (ƒt(xt)) is calculated that results from selecting xt when performing the step, where ƒt is a cost function. A minimum possible cost (ƒt(x*t)) associated with the selection of x* is then found and the difference between the resulting cost (ƒt(xt)) and the minimum possible cost (ƒt(x*t)) is determined. A direction of movement from xt to xt+1 is selected and a subsequent step that relies on the section of xt+1 is then performed.
    Type: Application
    Filed: June 30, 2010
    Publication date: January 5, 2012
    Applicant: IBM CORPORATION
    Inventors: Elad Eliezer Hazan, Nimrod Megiddo
  • Publication number: 20120005448
    Abstract: Management of a UNIX-style storage pools is enhanced by specially managing one or more memory management inodes associated with pinned and allocated pages of data storage by providing indirect access to the pinned and allocated pages by one or more user processes via a handle, while preventing direct access of the pinned and allocated pages by the user processes without use of the handles; scanning periodically hardware status bits in the inodes to determine which of the pinned and allocated pages have been recently accessed within a pre-determined period of time; requesting via a callback communication to each user process to determine which of the least-recently accessed pinned and allocated pages can be either deallocated or defragmented and compacted; and responsive to receiving one or more page indicators of pages unpinned by the user processes, compacting or deallocating one or more pages corresponding to the page indicators.
    Type: Application
    Filed: June 30, 2010
    Publication date: January 5, 2012
    Applicant: IBM CORPORATION
    Inventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
  • Publication number: 20120001228
    Abstract: An example embodiment of a strained channel transistor structure comprises the following: a strained channel region comprising a first semiconductor material with a first natural lattice constant; a gate dielectric layer overlying the strained channel region; a gate electrode overlying the gate dielectric layer; and a source region and drain region oppositely adjacent to the strained channel region, one or both of the source region and drain region are comprised of a stressor region comprised of a second semiconductor material with a second natural lattice constant different from the first natural lattice constant; the stressor region has a graded concentration of a dopant impurity and/or of a stress inducing molecule. Another example embodiment is a process to form the graded impurity or stress inducing molecule stressor embedded S/D region, whereby the location/profile of the S/D stressor is not defined by the recess depth/profile.
    Type: Application
    Filed: September 12, 2011
    Publication date: January 5, 2012
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION (IBM), GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yung Fu CHONG, Zhijiong LUO, Judson Robert HOLT
  • Publication number: 20110310964
    Abstract: According to one embodiment of the present invention, a method for echocardiogram view classification is provided. According to one embodiment of the present invention, a method comprises: obtaining a plurality of video images of a subject; aligning the plurality images; using the aligned images to generate a motion magnitude image; filtering the motion magnitude image using an edge map on image intensity; detecting features on the motion magnitude image, retaining only those features which lie in the neighborhood of intensity edges; encoding the remaining features by generating, x, y image coordinates, a motion magnitude histogram in a window around the feature point, and a histogram of intensity values near the feature point; and using the encoded features to classify the video images of the subject into a predetermined classification.
    Type: Application
    Filed: June 19, 2010
    Publication date: December 22, 2011
    Applicant: IBM Corporation
    Inventors: David James Beymer, Ritwik Kailash Kumar, Tanveer Fathima Syeda-Mahmood, Fei Wang
  • Publication number: 20110295995
    Abstract: A method and system for controlling load admission rate of an application server is provided. In the method, actual heap utilization and load admission rate of the application server in current control cycle are detected; based on the detected actual heap utilization and load admission rate, load characteristics variation parameters of the application server are estimated; and control gain of a feedback controller is calculated based on the load characteristics variation parameters; the feedback controller calculates desired load admission rate of the application server in next control cycle by using the calculated control gain. The load admission rate of the application server can be adaptively controlled by tracking changes in workload characteristics of the application server, such that the actual heap utilization of the application server is maintained at or close to target heap utilization.
    Type: Application
    Filed: May 25, 2010
    Publication date: December 1, 2011
    Applicant: IBM CORPORATION
    Inventors: Yixin Diao, Xiao Lei Hu, Michael Joseph Spreitzer, Asser Nasreldin Tantawi, Rui Xiong Tian, Hai Shan Wu
  • Publication number: 20110270770
    Abstract: The likelihood of a problem report being escalated to a critical status in a customer service environment is predicted by receiving historical Problem Management Records for which associated problems have been resolved and final criticality statuses have been determined, analyzing the historical Problem Management Records using at least one trainable data mining process to produce a prediction output for each historical Problem Management Record, validating the prediction output against the final criticality statuses, training the data mining process according to the validation, and, subsequently, analyzing an unresolved Problem Management Record by the trained analysis module to produce a prediction indicator and a confidence indicator for unresolved Problem Management Record to be re-classified as critical status. The unresolved Problem Management Record is escalated to critical status level responsive to the prediction indicator and the confidence indicator exceeding a predetermined threshold.
    Type: Application
    Filed: April 30, 2010
    Publication date: November 3, 2011
    Applicant: IBM Corporation
    Inventors: Russell E. Cunningham, Jason W. Hayes, Satish K. Rao
  • Publication number: 20110261259
    Abstract: A method controls one or more attributes of a secondary video stream for display in combination with a primary video stream. The method comprises: identifying a primary video stream; identifying a secondary video stream; assigning one or more settings for one or more attributes of said secondary video stream to a predetermined set of one or more user identifiers; identifying the user identifier associated with a given video processing module; determining the one or more attribute settings assigned to the user identifier; and processing the secondary video stream for display in combination with the primary video stream in accordance with the one or more attribute settings for the user identifier.
    Type: Application
    Filed: December 1, 2010
    Publication date: October 27, 2011
    Applicant: IBM CORPORATION
    Inventors: Christopher Phillips, Matthew Whitbourne
  • Publication number: 20110246482
    Abstract: According to one embodiment of the present invention, a method for cross-service tagging is provided. The method includes creating connections to multiple applications, each application having multiple entities. Relationships are determined between the entities within a single application and between entities across multiple applications. A tag is associated with a selected one of the entities in a first one of the multiple applications. Entities in other applications besides the first application are identified that are related to the selected entity, based on the determined relationships. The tag is propagated across multiple applications by associating the tag with the identified entities in the other applications. According to a second embodiment of the present invention, a method for inferring tags suggestions is provided. This method includes analyzing email messages to create keywords from text analysis, from bringing content and tags from other email messages or directory applications.
    Type: Application
    Filed: March 31, 2010
    Publication date: October 6, 2011
    Applicant: IBM CORPORATION
    Inventors: Hernan Badenes, Julian Ariel Cerruti, Stephen Michael Dill, Julia Haven Grace, Nicolas Lanaro, Jerald Thomas Schoudt, John C. Tang, Eric Wilcox
  • Publication number: 20110223737
    Abstract: Some example embodiments of the invention comprise methods for and semiconductor structures comprised of: a MOS transistor comprised of source/drain regions, a gate dielectric, a gate electrode, channel region; a carbon doped SiGe region that applies a stress on the channel region whereby the carbon doped SiGe region retains stress/strain on the channel region after subsequent heat processing.
    Type: Application
    Filed: May 23, 2011
    Publication date: September 15, 2011
    Applicants: GLOBALFOUNDRIES SINGAPORE PTE. LTD., INTERNATIONAL BUSINESS MACHINES CORPORATION (IBM)
    Inventors: Jin Ping LIU, Judson Robert HOLT
  • Publication number: 20110185361
    Abstract: An illustrative embodiment of a computer-implemented process for interdependent task management selects a task from an execution task dependency chain to form a selected task, wherein a type selected from a set of types including “forAll,” “runOnce” and none is associated with the selected task and determines whether there is a “forAll” task. Responsive to a determination that there is no “forAll” task, determines whether there is a “runOnce” task and responsive to a determination that there is a “runOnce” task further determines whether there is a semaphore for the selected task. Responsive to a determination that there is a semaphore for the selected task, the computer-implemented process determines whether the semaphore is “on” for the selected task and responsive to a determination that the semaphore is “on,” sets the semaphore “off” and executes the selected task.
    Type: Application
    Filed: October 26, 2010
    Publication date: July 28, 2011
    Applicant: IBM CORPORATION
    Inventors: Walfrey Ng, Chenfei Song
  • Publication number: 20110185132
    Abstract: In a computer system supporting memory compression and wherein data is stored on a disk in a different compressed format, and wherein an IOA (input/output adaptor)/IOP (input/output processor) selectively reads from and writes to a main memory through a direct memory access (DMA) operation, a method for transmitting compressed data from the IOA/IOP to the main memory includes reserving a set of free memory sectors to contain the data in said main memory, sending to the IOA/IOP addresses of said memory sectors, copying the data from the IOA/IOP to said memory sectors using said DMA operation, constructing at the IOA/IOP compressed memory directory information defining how and where the data is stored in memory, sending the memory directory information to a memory controller, and storing the memory directory information in the compressed memory directory structure.
    Type: Application
    Filed: April 8, 2011
    Publication date: July 28, 2011
    Applicant: IBM Corporation
    Inventors: Caroline Benveniste, Vittorio Castelli, Peter A. Franaszek
  • Publication number: 20110179197
    Abstract: A method of transmitting compressed data from a main memory to an input/output adaptor (IOA)/input/output processor (IOP), includes sending compressed memory directory information to the IOA/IOP and copying a content of the memory to the IOA/IOP using a direct memory access (DMA) operation, without decompressing the data.
    Type: Application
    Filed: March 31, 2011
    Publication date: July 21, 2011
    Applicant: IBM Corporation
    Inventors: Caroline Benveniste, Vittorio Castelli, Peter A. Franaszek
  • Publication number: 20110170266
    Abstract: a 4D device comprises a 2D multi-core logic and a 3D memory stack connected through the memory stack sidewall using a fine pitch T&J connection. The 3D memory in the stack is thinned from the original wafer thickness to no remaining Si. A tounge and groove device at the memory wafer top and bottom surfaces allows an accurate stack alignment. The memory stack also has micro-channels on the backside to allow fluid cooling. The memory stack is further diced at the fixed clock-cycle distance and is flipped on its side and re-assembled on to a template into a pseudo-wafer format. The top side wall of the assembly is polished and built with BEOL to fan-out and use the T&J fine pitch connection to join to the 2D logic wafer. The other side of the memory stack is polished, fanned-out, and bumped with C4 solder. The invention also comprises a process for manufacturing the device.
    Type: Application
    Filed: January 8, 2010
    Publication date: July 14, 2011
    Applicant: IBM Corporation
    Inventors: Wilfried Haensch, Roy R. Yu
  • Publication number: 20110161976
    Abstract: A method efficiently dispatches/completes a work element within a multi-node, data processing system that has a global command queue (GCQ) and at least one high latency node. The method comprises: at the high latency processor node, work scheduling logic establishing a local command/work queue (LCQ) in which multiple work items for execution by local processing units can be staged prior to execution; a first local processing unit retrieving via a work request a larger chunk size of work than can be completed in a normal work completion/execution cycle by the local processing unit; storing the larger chunk size of work retrieved in a local command/work queue (LCQ); enabling the first local processing unit to locally schedule and complete portions of the work stored within the LCQ; and transmitting a next work request to the GCQ only when all the work within the LCQ has been dispatched by the local processing units.
    Type: Application
    Filed: December 30, 2009
    Publication date: June 30, 2011
    Applicant: IBM CORPORATION
    Inventors: Benjamin G. Alexander, Gregory H. Bellows, Joaquin Madruga, Barry L. Minor
  • Publication number: 20110161608
    Abstract: Disclosed are a method, a system and a computer program product of operating a data processing system that can include or be coupled to multiple processor cores. In one or more embodiments, each of multiple memory objects can be populated with work items and can be associated with attributes that can include information which can be used to describe data of each memory object and/or which can be used to process data of each memory object. The attributes can be used to indicate one or more of a cache policy, a cache size, and a cache line size, among others. In one or more embodiments, the attributes can be used as a history of how each memory object is used. The attributes can be used to indicate cache history statistics (e.g., a hit rate, a miss rate, etc.).
    Type: Application
    Filed: December 30, 2009
    Publication date: June 30, 2011
    Applicant: IBM CORPORATION
    Inventors: Gregory H. Bellows, Joaquin Madruga, Ross A. Mikosh, Barry L. Minor
  • Publication number: 20110161734
    Abstract: Disclosed are a method, a system and a computer program product of operating a data processing system that can include or be coupled to multiple processor cores. In one or more embodiments, an error can be determined while two or more processor cores are processing a first group of two or more work items, and the error can be signaled to an application. The application can determine a state of progress of processing the two or more work items and at least one dependency from the state of progress. In one or more embodiments, a second group of two or more work items that are scheduled for processing can be unscheduled, in response to determining the error. In one or more embodiments, the application can process at least one work item that caused the error, and the second group of two or more work items can be rescheduled for processing.
    Type: Application
    Filed: December 31, 2009
    Publication date: June 30, 2011
    Applicant: IBM CORPORATION
    Inventors: Benjamin G. Alexander, Gregory H. Bellows, Joaquin Madruga, Barry L. Minor
  • Publication number: 20110161975
    Abstract: A method for efficient dispatch/completion of a work element within a multi-node data processing system. The method comprises: selecting specific processing units from among the processing nodes to complete execution of a work element that has multiple individual work items that may be independently executed by different ones of the processing units; generating an allocated processor unit (APU) bit mask that identifies at least one of the processing units that has been selected; placing the work element in a first entry of a global command queue (GCQ); associating the APU mask with the work element in the GCQ; and responsive to receipt at the GCQ of work requests from each of the multiple processing nodes or the processing units, enabling only the selected specific ones of the processing nodes or the processing units to be able to retrieve work from the work element in the GCQ.
    Type: Application
    Filed: December 30, 2009
    Publication date: June 30, 2011
    Applicant: IBM CORPORATION
    Inventors: Benjamin G. Alexander, Gregory H. Bellows, Joaquin Madruga, Barry L. Minor